Symmetric multiprocessing

A symmetric multiprocessor system (SMP), in the information technology, a multi-processor architecture in which two or more identical processors share a common address space. This means that each processor with the same (physical) address the same memory cell, or the same peripheral registers addressed. Most multiprocessor systems today are SMP architectures.

An SMP architecture allows to dynamically distribute the processes running on all available processors - on the other hand, each CPU has the asymmetric multiprocessing a task will be assigned to (eg leads CPU0 operating system calls and CPU1 user processes ), since not all tasks on each processor can be performed. But there are also application domains (eg, control technology with hard real-time requirements), in which a static mapping of processes is more advantageous on an SMP architecture.

If there are no divisions of the hardware used in partitions or CPU sets, an SMP system as a single system image ( SSI) is called - only one operating system kernel controls the entire machine.

Details

Symmetric multiprocessing since the late 1980s, the standard architecture for multiprocessor machines with up to 16 CPUs.

The requirement that each CPU can execute any process must, but results in larger systems mean that the memory is the bottleneck. With each additional CPU, the relative performance gain decreases as the storage subsystems can not deliver fast enough data in order to fill all the available CPUs.

Another problem with SMP is the CPU hopping, change the processes constantly between the individual CPUs. Normally, this would be no problem, but there often CPUs with very large and multiple staggered caches used in SMP systems to use to reduce the already -described utilization of the storage system, the rapid change of the running processes also leads to a performance degradation due to a so-called cache thrashing. This refers to the constant change of the cache contents by different processes, which usually access to different data areas. However, it is the effect counteracted by assigning a higher affinity of the processes to the respective executing CPU.

In further developments, such as the NUMA ( Non-Uniform Memory Architecture), these problems are reduced.

In principle, all modern CPU architectures are more or less suitable for use in SMP systems. There are differences only in the required additional hardware and the expected increase in performance per CPU. While with some CPU variants already relatively simple 2 - or 4-way systems can be built, since the CPU bus is already part of the required functionality are implemented (eg all Intel systems with GTL bus) are, in other systems relatively complex point-to -point connections required ( AMD K7 and DEC / Compaq / HP Alpha with EV6 bus). Currently, the manufacturers go for performance reasons on to integrate the required memory controller into the CPU. In turn, it makes sense to integrate multiple CPU cores on the chip, since a single core can not always utilize the available data rate of the memory system. Such multi-core processors should not be confused with Hyper -Threading -enabled processors, as this is completely independent cores with associated infrastructure ( L1/L2-Caches, FPU, etc.).

• Computer Architecture