Systembus

The term system is summarizes the various data rails ( buses ), the CPU communicates via a microcomputer with their environment. Usually three such buses are distinguished: the data bus, the address bus and the control bus.

System types

There are three different system types that differ in their timing. The specification of the timing behavior is dependent on the manufacturer and is also referred to as the system bus protocol. The two main types form synchronous and asynchronous system buses. The former are clocked so that the transfer of data can only be earned with a clock edge ( in either direction ). The latter are untimed and typically use a handshake protocol to control the acquisition of data. The third type of bus represents an intermediate solution: While the bus is clocked, but the additional use of control lines enables additional wait cycles to be able to connect and slow components to the bus can. This type of bus is referred to, therefore, as a semi- synchronous. Most modern microprocessors using a semi- synchronous system.

Access to the system bus

Since many different components to access to the system, this access must be controlled. One speaks in this context of Bus Arbitration Control. This control is usually done by a special device ( eg an arbiter or coprocessor ). To control are the three signals BREQ ( bus request ), BGRT (Bus Grant) and BGA (Bus Grant Acknowledge). This process is also referred to as 3- line handshake.

The process is basically as follows. The processor had just held the control of the system. For example, he could have created an address on the address bus and now just read the so addressed via the data bus. At the same time an external component notifies the processor by means of the BREQ signal that it requires access to the system. Once the processor with the reading of the data on the data bus is ready, he edited the BREQ signal and provides the component access by BGRT. The component responds (possibly optional) with BGA on the permit and shall communicate with the processor and other components that it has taken control of the bus. Since external components usually are allowed to access a higher priority on the bus as the processor itself, the processor must submit requests for pending control mostly.

But what happens when multiple BREQ signals are present at the same time? To handle such situations, it is usually an arbiter module one, that handles requests, sorted by priority and then passes sequentially to the processor. The external components then contact no longer directly using BREQ to the processor, but have control lines to the arbiter which controls everything else.

System bus

The interface between the processor and system bus is called the system bus. It usually contains buffer register for data and addresses that can be organized may as FIFO. The latter is especially the case when the processor is clocked differently than the system, to allow a more efficient buffering.

For coupling to the bus so-called tri-state gates are used. These are in a position, in addition to the levels of low and high take a high-impedance state at the output special to disconnect the processor from the system when other devices are able to access it.

• Computer Architecture
• Bus system