SystemC

SystemC is a modeling and simulation language especially for the development of complex electronic systems that include both hardware and software components.

In contrast to pure hardware description languages ​​( such as VHDL and Verilog HDL) SystemC is primarily used for modeling at even higher levels of abstraction, thus simulations can be faster by a factor of 100 to 1000 and even longer programs that run on the hardware described, can be simulated graphically. However, the modeling of synthesizable circuits on the so-called register transfer level are possible using SystemC as a substitute for VHDL or Verilog. More driving advantages of SystemC are next on the one hand, the free availability as open source and also the relationship to popular programming language C .

SystemC is not a standalone language, but a (class) library for C . It expands the language using macros and functions to provide the necessary resources to additional modeling typical properties of hardware can as synchronization, concurrency and interprocess communication. This brings a SystemC the disadvantage of a syntactic overheads, do not have the hardware description languages. But the developer is clearly in free expression.

SystemC is suitable, such as the modeling language E, for the modeling of protocols and peripherals in order to use it to verify the correctness of a digital circuit. However, SystemC is not only a modeling language, but also their own simulation kernel. This is in the SystemC library included (eg: in each reference implementation of the OSCI ) so that generated by compiling a system source code of an executable simulator with the behavior of the source code. However, SystemC is also supported by commercial simulation tools like Modelsim.

Many universities are working out of efficient programs for circuit synthesis from SystemC models. Some companies offer solutions that can generate netlists for ASICs or FPGAs from certain SystemC code. In 2005, the version 2.1 of the SystemC reference description of the international engineering association IEEE has been ratified as a standard (IEEE 1666-2005 ). This standard represents the current LRM ( Language Reference Manual ) represents and is at the IEEE available for free download (see links). In 2007, the open-source Referenzimplentierung the OSCI (Open SystemC Initiative) was to version 2.2 updated to fully with the IEEE 1666 LRM to be compliant.

Syntax

Since SystemC is a class library for C only typical for SystemC constructs are indicated here.

Modules

Modules can be used to structure complex systems into manageable parts. They are building blocks that are accessible to the outside via ports and can in turn contain modules. The syntax is

SC_MODULE (module name) { / / Contents of module }; An instance of the module is through the constructor

SC_CTOR (module name) {. . . } realized.

Signals and ports

Ports form the interface of the module to the outside. There are three types of ports and a fourth type of signals:

Sc_in PortInName; / / Input sc_out PortOutName; / / Output sc_inout PortInOutName; / / Bidirectional sc_signal signame; / / Signal processes

The functionality of the modules is formed by processes. There are three types of processes.

Method processes are invoked when a signal from the sensitivity list changes and passed after execution control back to the simulator back. by

SC_METHOD (function name); is a specific function that must be declared in the module previously installed. The sensitivity list is

Sensitive << Signal1 << Signal2. . . generated.

In contrast to method - thread processes - processes are started only once and always go through again the same loop, serve in the wait ( ) command to temporarily turn off.

SC_THREAD (function name); Clocked -threaded processes are synchronous thread processes whose actions are not visible until the next clock edge. In contrast to the threaded processes no indication of the sensitivity list but the second argument is selected when calling

SC_CTHREAD (function name, clock edge ); specifies which edge of the clock signal triggers the process.

Example

An adder in SystemC:

# include " systemc.h " SC_MODULE ( adder ) / / module declaration (a type of class) {    sc_in a, b; / / Two input ports (a and b )    sc_out sum; / / A output port    SC_CTOR ( adder )    {       SC_THREAD ( doit );       sensitive << a << b;    }       void doit ()       {         while (true)         {           sum.write ( A.Read () b.read ());           wait ();         }       } }; see also

  • Just Another Hardware Definition Language
  • ABEL
  • SystemVerilog
  • SpecC
  • Electronic Design Automation
Institute of Electrical and Electronics Engineers Advanced Boolean Expression Language
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