Three-dimensional integrated circuit

Under 3D integration is understood in the electronic integrated circuit ( IC chip) in which the active electronic components are horizontally so integrated vertically in two or more layers, that is, connected to a single circuit, a so-called three-dimensionally integrated circuit ( 3D IC). In the semiconductor industry, this technology is treated as a promising way to continue the trend of more compact and more powerful electronic devices, and is therefore followed in the form of many sometimes very different approaches. At present ( end of 2011) three-dimensionally integrated circuits, however, are not yet widely used.

  • 8.1 Literature
  • 8.2 External links
  • 8.3 Notes and references

Difference of 3D ICs and 3D Packaging

3D Packaging (English 3D packaging) saves space by stacking separate chips in a single package. With this as a system -in-package (SiP ), or chip -stack multi-chip modules known technique, the individual ICs are not integrated into a single circuit. They continue to communicate outside of the chip via electrical signals as well as if they are mounted in different packages to a printed circuit board. Unlike a 3D IC acts as a single IC. All components on all levels chip communicate with each other within the 3D - IC, depending on how it is designed for vertically and horizontally. A 3D IC thus behaves in a 3D packaging similar to a system-on -a-chip to a circuit board.

Manufacturing techniques

The following are the four most common ways to produce 3D integrated circuits listed:


The traditional scaling of semiconductor chips improves the signal propagation time. However, the further scaling of current manufacturing and chip design technologies has become more difficult, partly because of the limitations on the maximum power density and on the other because the electrical connections have themselves become different from the transistors are not faster. For this reason, 3D - integrated circuits have been proposed to overcome the challenges in further scaling by stacking traditional 2D integrated circuits and connect in the third dimension. This promises a faster communication as compared to a planar arrangement. With 3D ICs many important advantages are connected, including:

  • Smaller footprint: For 3D ICs more functional components fit on a lower surface of the component support, for example on the board. This allows new generations of small but powerful devices.
  • Lower costs: The size and the minimum achievable defect density limit the theoretical maximum yield of integrated circuits. Therefore, the division of larger 2D ICs into a plurality of smaller sub- chips, and their stacking in 3D ICs can increase the yield, thereby reducing the manufacturing cost. This is especially true if the partial chips were tested before bonding individually on their function. Therefore, the cost advantage is less true for wafer -on- wafer method.
  • Heterogeneous integration: 3D ICs offer the possibility to integrate part chips of different manufacturing processes. This makes it possible to optimize the production of the individual components to a much higher degree than if they are produced together on one chip. Moreover, what is meant is that you can combine components of different and incompatible manufacturing techniques in a 3D IC.
  • Shorter signal paths and reduced power consumption: Reducing the power consumption generally results in an increase in battery life. Further characterized but also generates less heat, this will lead to low demands on the cooling system and, in turn, allows for smaller devices. It should be remembered, however, that tends to be worse by the stacking of the heat dissipation, so that in 3D ICs, the power consumption must be generally lower and the incidence of local heat centers generally more attention should be paid. In addition to the overall reduction of supply voltages in scaling in 3D ICs lower power consumption is achieved by shorter signal paths. Thus, the power of signals which is now left on the chip to a factor of 10 to 100 can be reduced. Shorter electrical connections also reduce the power required, as this occur less parasitic capacitances.
  • Design / Construction: The use of an additional dimension allows a higher order in the connectivity of the components and thus new opportunities in construction or design.
  • Bandwidth: The 3D integration allows for a large number of vertical connections between the individual chip layers. This enables the production of broadband data buses between the functional blocks in different planes. A typical example would be a stack of the processor and memory, wherein the cache memory is placed on the processor. This arrangement allows buses with much greater bandwidth than is currently typical buses 128 or 256 bits. Large buses in turn relieve the memory -wall problem, that is, the fact that today's processors often have to wait for memory accesses, and so their performance can not really take advantage of.


Since this technology is new, it has to overcome new challenges, including:

Design methods

Depending on the layout of the functional blocks to the individual sub chips can be divided into two design methods: the gate-level and the block-level integration. The gate-level integration is here confronted with various challenges and currently seems less practical than the block - level integration.

Gate-level integration

With integration of the circuit on gate or transistor level, the standard cells (function blocks) are split among multiple chips. This integration variant promises a reduction in the conduction paths and great flexibility. However, the advantage of shorter cable paths, only applies if the partial function blocks do not fall below a certain size. Because on the other side is the high number of required vias for connections between the part of the chip. A large number of plated-through holes accepts expensive chip area and increasing the complexity of the design. The gate-level integration requires 3D - place-and- route software, which are not currently available. Further implies the allocation of a function block to a plurality of sub chips that the blocks can not be fully tested prior to assembly of the 3D - IC. So can cause a partial chip failure of the whole 3D ICs, and thus several good portion of chips, the failure of an area, so that the yield drops further. Furthermore, this method also enhances the impact of process variations, particularly variation between sub- chips. Therefore, the yield can be lower in a 3D layout than in a 2D IC of the same circuit. Furthermore, the gate-level integration forces a redesign of existing designs, mainly because existing IP cores and EDA software currently available are not available for 3D integration.

Block-level integration

In this method, only full functional blocks are distributed to the individual chips. The functional blocks include usually the bulk of the interconnect network and are connected via a small number of "global" compounds linked to each other. For this reason, the block-level integration promises a reduction of surplus vias. Sophisticated 3D systems in which heterogeneous individual chips are combined together, require different manufacturing processes at different technology nodes for fast or low-power logic, different types of memory, analog and RF circuits, etc. It therefore seems the block-level integration, the separate and optimized manufacturing processes enables critical to the success of 3D integration. In addition, this technique can facilitate the transition from the current 2D to 3D IC design. Basically, 3D -enabled software tools for the division of function blocks on the individual chips and for thermal analysis are necessary. The respective single chip can be developed with available (possibly customized ) 2D tools and 2D blocks. The benefit of a wide availability of reliable IP cores, since it is easier to use available 2D IP cores and to place the obligatory vias in the free space between the blocks, instead of the IP blocks neuzugestalten and embed it vias. Design for testability structures are an integral part of the IP blocks and therefore can be used to facilitate testing of ICs 3D. Moreover, many critical paths may be incorporated into the 2D blocks, this limits the effect on the yield by variations in the manufacture of the vias, and between the individual chips.

Notable 3D ICs

Presented as early as 2004 Intel a 3D version of its Pentium 4 CPU. The stacked chip is made of two single chips in which each of which was the side with the active components articulate and connected to each other, allowing a dense via structure. Vias to the back side of the individual chips have been used for the external connection and the power supply signal. For the placement and wiring diagram in 3D designers arranged the functional blocks of each chip with the aim for power reduction and performance improvement in manually. The distribution of large and high-performance blocks and a careful re-arrangement allows to limit thermal hotspots. The 3D design allowed compared to the 2D Pentium 4 a performance increase of 15 % (due to remote pipeline stages ) and energy savings of 15 % also (due to distant repeaters and reduced wiring costs ).

The teraflop research chip was introduced in 2007 by Intel and is an experimental 80 - core design with stacked storage units. Due to the high demand for memory bandwidth a traditional IO approach 10 to 25 W would need. In order to achieve an improvement to the Intel designers have implemented an on Siliziumdurchkontaktierung (german though silicon via TSV ) based memory bus. Each core is connected to a storage level of the SRAM chips on a 12-GB/s-Verbindung. This results in a total bandwidth of 1 TB / s and requires only 2.2 W.

A rather academic implementation of a 3D processor was presented in 2008 by employees or students by Professor Eby Friedman at the University of Rochester. The circuit operates at a clock frequency of 1.4 GHz and was designed for optimum vertical processing between the stacked chips, the 3D processor should provide capabilities that could not reach a traditional circuit in a plane. A challenge in the production of three-dimensional circuit was that all levels harmonious and undisturbed working without disturb information that is exchanged between the different levels, each other.


IntSim is an open source CAD program, 2D and 3D ICs can be simulated with the. It can be used also to predict the performance, size, number of wiring levels and the optimal size of wiring levels of 2D/3D-Chips based on different techniques and design parameters. Users can also study scaling trends and apply the program for the optimization of their chip designs.

Further reading material and sources