Transmeta Crusoe

Crusoe is a family of x86-compatible CPUs from Transmeta, which was used particularly for low-power notebooks and similar computers.

Transmeta developed to a new concept to make the x86 different CPU x86 compatible: A software solution called code - morphing emulated in real time on an x86 CPU. Since emulations are usually quite inefficient, constantly optimizes the Transmeta software during the term of the emulation of the running programs. The processor itself is a 128 -bit VLIW processor constructed much simpler than a conventional CPU x86 from Intel or AMD and therefore requires much less power, or produces much less heat.

In principle it may mimic any CPU architecture with the code - morphing software. However, it was limited when Crusoe on x86 commands including MMX. It would be theoretically possible, SSE or 3DNow! to emulate.

Successor of the Crusoe is the Efficeon.

Model data

TM3200

Was initially referred to as TM3120

  • L1 - Cache: 32 64 KB ( data instructions )
  • MMX
  • VLIW with code - morphing technique
  • Integrated North Bridge in CPU
  • Packaging: 474 Pin CBGA

TM5400

  • L1 - Cache: 64 64 KB ( data instructions )
  • L2 cache: 256 KB with processor clock
  • MMX, LongRun
  • VLIW with code - morphing technique
  • Integrated North Bridge in CPU
  • Packaging: 474 Pin CBGA

TM5500

  • L1 - Cache: 64 64 KB ( data instructions )
  • L2 cache: 256 KB with processor clock
  • MMX, LongRun
  • VLIW with code - morphing technique
  • Integrated North Bridge in CPU
  • Packaging: 474 Pin CBGA

TM5600

  • L1 - Cache: 64 64 KB ( data instructions )
  • L2 cache: 512 KB with processor clock
  • MMX, LongRun
  • VLIW with code - morphing technique
  • Integrated North Bridge in CPU
  • Packaging: 474 Pin CBGA

TM5700

  • L1 - Cache: 64 64 KB ( data instructions )
  • L2 cache: 256 KB with processor clock
  • MMX, LongRun
  • VLIW with code - morphing technique
  • Integrated North Bridge in CPU
  • Packaging: 399 Pin OBGA

TM5800

  • L1 - Cache: 64 64 KB ( data instructions )
  • L2 cache: 512 KB with processor clock
  • MMX, LongRun
  • VLIW with code - morphing technique
  • Integrated North Bridge in CPU
  • Packaging: 474 Pin CBGA

TM5900

  • L1 - Cache: 64 64 KB ( data instructions )
  • L2 cache: 512 KB with processor clock
  • MMX, LongRun
  • VLIW with code - morphing technique
  • Integrated North Bridge in CPU
  • Packaging: 399 Pin OBGA
Real-time Run time (program lifecycle phase) Transmeta Efficeon Northbridge (computing) IBM TSMC
782436
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