Verilog
Verilog HDL is VHDL next to the world's most widely used hardware description language.
History
Verilog HDL was originally designed in 1983/84 by Phil Moorby at Gateway Design Automation as a simulation language. The second important application is the synthesis of digital circuits. Gateway Design Automation was acquired in 1990 by Cadence Design Systems. Cadence was now the owner of the rights to Verilog and Verilog -XL logic simulator.
Parallel to Verilog HDL description language VHDL has become increasingly popular, and Cadence decided in 1995 to convert Verilog into a free standard, managed by the organization Open Verilog International ( OVI, also known as Accellera ). Verilog was submitted to the IEEE and adopted in the same year as IEEE Standard 1364-1995 ( Verilog -95).
By merging Verilog -A ( modeling language for analog circuits ) and Verilog to Verilog -AMS stands since 1998 ( first version ) also a relatively powerful language for analog / mixed - signal designs available. However, no synthesis tools are available for the analog range. For the digital domain Synopsys delivered in 1988, a synthesis tool for Verilog from.
Due to restrictions that have been criticized by users, the IEEE in 2001 published an extension of the standards are known as IEEE Standard 1364-2001 known as Verilog 2001.
In June 2002 was released SystemVerilog 3.0, an extension to the IEEE Standard 1364-2001. With SystemVerilog, it was now possible not only to describe hardware, but also to verify elegant. Verilog was thus ( briefly called HDVL English Hardware Description and Verification Language, ) through to the first SystemVerilog Hardware Description and Verification Language. Also in recent years constantly language extensions have been made.
Operation
Verilog HDL allows hardware (eg ICs) to describe at a higher level of abstraction than would be possible with a schematic entry program. The architecture, the performance and lower abstraction level at the gate level can be described.
Example of an AND gate (AND gate)
/ / This is a Verilog HDL comment / / Declaration of the variable as a simple line Wire result, a, b; / / There are 3 variants to describe a (bitwise ) AND gate / / Option 1 assign result = a & b; / / Continuous assignment / / Option 2 and instance name (result, a, b ); / / Instantiation of an existing module (in this case a built- primitive ) / / Option 3 always @ ( a or b) / / Behavior Description / / react to any change of a or b ( In combinatorial logic) begin result = a & b; end always @ ( a or b) / / alternative behavioral description / / react to any change of a or b ( In combinatorial logic) begin if (a ) then result = b; else result = 1'b0; end Example of a behavioral description of a flip-flop ( synthesized )
/ / Declarations reg register_value; / / As a register or memory variable wire reset, clock, set, en, datain; / / As a line / / Flip-flop with asynchronous reset, synchronous and synchronous Set Enable always @ ( posedge clock or negEdge reset) begin / / Register responds to positive clock edge or falling edge of reset. if (! reset) / / asynchronous reset if reset = LOW register_value < = 1'b0; else if (set) / / synchronous setting, when set to HIGH register_value < = 1'b1; else if ( s) / / synchronous Apply the value of datain if s = HIGH register_value < = datain; end In addition to the description of options for hardware Verilog HDL also offers features from other languages , which can be used eg for debugging or for providing a test environment. For example, it is possible to output text messages.
Hello module;
/ / Module declaration with the keyword "module"
- Harald wings: FPGA design using Verilog. Oldenbourg, München 2010, ISBN 978-3-486-59234-4.
- Bernhard Hoppe: Verilog. Modeling for synthesis and verification. Oldenbourg, Munich, etc. 2006, ISBN 3-486-58004-3.