VHDL

Very High Speed ​​Integrated Circuit Hardware Description Language (also VHSIC Hardware Description Language ), short VHDL is a hardware description language, similar to a programming language in which it is possible to describe text-based digital systems. VHDL is defined as an IEEE standard since 1987 and there are now some also standardized language extensions. In addition, there are language derivatives such as VHDL-AMS, with the aid of analogue or mixed-signal systems can be described.

  • 4.1 programming styles

History

VHDL was developed as part of the VHSIC initiative, which was set up by the U.S. government in 1980 to catch an incurred towards the private sector technology lag in the development of Very High Speed ​​Integrated Circuits. The language definition was the product of standardization efforts of a committee, in which most major CAD vendors and CAD users, but also organizations such as the IEEE, were represented. As a major North American clients then the U.S. Department of Defense (English Department of Defense ) VHDL made ​​to prevail. It demanded that all ASICs developed on their behalf after the September 30, 1988 would have to be documented in VHDL. However, it was only required that realistic behavioral descriptions would arise in VHDL. The implementation language - either VHDL or VerilogHDL the hitherto usual graphical input - remained open for the contractors. The goal was to at least unify the circuit documentation and to enable the simulation of complex digital system descriptions from various sources. The first commercial version was published in 1985. It arose from a collaboration between the companies IBM, Texas Instruments and Inter Metrics.

VHDL is standardized by the IEEE 1076 standard in 1993. Compared to the first standard in 1987 (IEEE 1076-1987 ) the language has been added, but also some of the old syntax constructs away and in a few cases changed the semantics of constructs.

An extension to the description on the analog electrical components and systems was achieved with AHDL. Currently, there are efforts to create a common language for the description of technical systems - see VHDL -AMS (VHDL analog / mixed signal). This is beyond the scope of purely electronic circuits and in addition to model mechanical elements, sensors and actuators, which will also be able to detect this with a system simulation.

Current EDA tools currently support the version of VHDL - 2002 and VHDL - 2008.

Operation

In VHDL you do not work with individual electronic components, but describes the desired behavior of a circuit at a higher level of abstraction. VHDL allows the rapid development of large and complex circuits (eg microprocessor with 20 million transistors), requiring high efficiency (in time as well as economically ) and supports the developer in any work.

Thus, a system can be simulated, synthesized, and finally a netlist can be created. A verification is possible both through a comprehensive simulation and formal.

From the netlist can create masks for the production of MPGAs ( mask programmable gate array) or similar LSI (Large scale integration ) chips are produced or it may (after conversion into a suitable Bitstream ) directly into a FPGA ( Field Programmable Gate Array) or CPLD ( Complex Programmable Logic Device) are loaded.

In addition to VHDL Verilog and ABEL exist. The world's most popular hardware description languages ​​VHDL and Verilog.

VHDL has become the " de facto standard " in Europe, the U.S., however, Verilog is the language most commonly used.

Efficient synthesis and functional VHDL code

It is necessary to distinguish between synthesefähigem and functional code because there are constructs that although they can be simulated, but can not be translated into real hardware and thus in a netlist. What is actually from the broad spectrum of functional VHDL synthesizable VHDL code, determined primarily Selected for VHDL synthesis translation program ( synthesis tool). Functional, not synthesizable code is mainly used in the circuit simulation and creation of so-called testbenches, partly also to consider new methods such as the behavior of interface protocols in advance.

Produce synthesis -capable VHDL code is more complex rule, and the developer should focus particularly on large parts of the voice capabilities of VHDL consciously renounce and know the target hardware and its exact properties closer. For example VHDL code for input and output through the operating system ( textio ) such as the reading and writing of files or the output of text on the screen is not capable of synthesis.

ENTITY IS DFlipflop      PORT (D, Clk: IN bit;           Q: OUT bit);    END DFlipflop;    ARCHITECTURE OF Behav DFlipflop IS        CONSTANT T_Clk_Q: time: = 4:23 ns;    BEGIN        PROCESS        BEGIN           WAIT UNTIL Clk'EVENT AND Clk'Last_Value = '0 'AND Clk = '1';           Q < = D AFTER T_Clk_Q;        END PROCESS;    END Behav; Example: D flip-flop ( behavioral ) can be synthesized, but " AFTER T_Clk_Q " is ignored    ENTITY IS DFlipflop      PORT (D, Clk: IN bit;           Q: OUT bit);    END DFlipflop;    ARCHITECTURE OF Behav DFlipflop IS        CONSTANT T_Clk_Q: time: = 4:23 ns;    BEGIN        PROCESS        BEGIN           WAIT UNTIL Clk'EVENT AND Clk = '1 ';           Q < = D AFTER T_Clk_Q;        END PROCESS;    END Behav; Example: D flip-flop ( behavioral ) synthesized, asynchronous reset    ENTITY IS DFlipflop      PORT (D, Clk, nResetAsync: IN bit;           Q: OUT bit);    END DFlipflop;    ARCHITECTURE OF Behav DFlipflop IS    BEGIN        PROCESS (Clk, nResetAsync )        BEGIN           IF nResetAsync = '0 ' THEN              Q < = '0 ';           ELSIF Clk'EVENT AND Clk = '1 ' THEN              Q < = D;           END IF;        END PROCESS;    END Behav; Example: D flip-flop ( behavioral ) synthesized, synchronous reset    ENTITY IS DFlipflop      PORT (D, Clk, nResetSync: IN bit;           Q: OUT bit);    END DFlipflop;    ARCHITECTURE OF Behav DFlipflop IS    BEGIN        PROCESS (Clk )        BEGIN           IF Clk'EVENT AND Clk = '1 ' THEN              IF nResetSync = '0 ' THEN                 Q < = '0 ';              ELSE                 Q < = D;              END IF;           END IF;        END PROCESS;    END Behav; Example: Other Architecture ( Manufacturer Library )     LIBRARY VendorLib;     ARCHITECTURE OF vendor DFlipflop IS        COMPONENT Dff PORT (D, Clk: IN bit; Qout: OUT bit); END COMPONENT;     BEGIN        Ff1: Dff PORT MAP ( D = > D, Clk => Clk, Qout => Q);        FOR ALL: Dff USE ENTITY VendorLib.Component.Dff;     END vendor; Simulation and verification of VHDL code

Meanwhile, VHDL has become established as the standard for the simulation models of intellectual property ( IP). In a simulation model of the actually to be tested and synthesizable VHDL code or VHDL module is embedded and simulated the hardware question in a so-called ' test bench ' as faithfully as possible. In this case, the simulation model is usually written in a non- synthesizable VHDL, that allows the modeling of the time behavior and certain physical parameters of the external circuit components.

An example will illustrate this process:

  • When creating a SDRAM controller, a circuit for controlling SDRAM memory modules, the SDRAM is simulated as closely as possible like the real SDRAM hardware with its memory and its temporal behavior in the simulation model. Thus, the controller can be simulated in its logical function and the behavior in the temporal extreme conditions can be verified without the need for real hardware would be necessary. If necessary, the SDRAM controller is operatively adapted accordingly in order to meet the simulation conditions. Only when this simulation is successful, the thus generated SDRAM controller hardware, for example, in an FPGA, in combination with 'real' SDRAM modules is put into operation. Thus, the development process of IP cores is largely independent of specific hardware.

The creation of good testbenches that allow such statements, it is a most underestimated task that makes up about 50 % of the total development time for IP cores. It is, however, in addition to a systematic approach in the development, much more efficient than early with mostly functioning not immediately circuit parts to go on real hardware - which can be verified in all its parameters will be difficult and cumbersome.

Next to distinguish different types of simulation in the simulation:

  • A pure behavioral simulation ( engl. behavioral simulation ) of the to-deploy IP core. The functional correlations in the circuit are always checked. For example, if logical combinations of individual signals fit. The advantage is the low computational complexity, which temporally longer sections can be simulated.
  • A simulation of the finished placed IP core ( engl. simulation post- fit ). Here, the IP core is first synthesized, placed and routed, the net list and the associated run-time information of the destination hardware may be determined from the finished circuitry. The application of run-time parameters in the VHDL code ( engl. back annotation ) is either taken over by appropriate tools that generate it does not synthesizable VHDL code, or it is done directly in the simulation program. The advantage is the more accurate model to recognize, for example, timing problems in the target hardware already in the simulation can. A disadvantage is the high computational effort involved and even on fast computers very long simulation times, which could, depending on the complexity of the circuit in the range of a few days.

It can further be distinguished between testbenches with its own fault detection and test benches that represent only the pure time. In the first case to existing tests due to fixed decisions ( " test vectors " ) are defined in the testbench and automatically determined by appropriate text output. The creation of these testbenches is more expensive, but offers the advantage of being able to check in later changes easier the changes in the implementation of fully and safely ( engl. regression test). In the second case, the circuit to be simulated in their time behavior ( engl. wave diagram ) is only represented without an automatic evaluation of the output is performed. The decision as to whether the behavior of the circuit is correct, is for the person who needs to check this timing manually. The advantage of this method is the simplicity in creating the testbenches, which is why it is mainly used in simple circuits. The disadvantage is that this error in the implementation by the manual examination can be easily overlooked, especially in complex circuits.

Skeleton of a VHDL block

ENTITY block name IS        GENERIC (parameter list, optional);                - This statement allows the model-dependent transfer                  Parameters (eg delay times ) for a block;        PORT ( interface list, optional);                - Here the signal interface of the block are outward                  defined; The following modes are possible IN, OUT, INOUT, ​​BUFFER;                - At this point several declarations may be made                  which can be used in different architecture hulls                  which include subroutines, type declarations,                  Constant declarations and signal declarations;        BEGIN (Click, optional);                - Here can stand instructions that apply to all architecture hulls                  be carried out; which shortens the architecture description,                  as listed in block declarations statements must                  are no longer in the architecture hulls;        END block name;                - End of module declaration Architecture Hull:

ARCHITECTURE OF fuselage Name Block Name IS           - At this point can optionally various declarations for             Types, constants and signals are made             In contrast to the block declarations these are here             valid only for the present architecture hull;        BEGIN           - Instructions that the behavior or structure of the             Block describe;        END hull name; programming styles

The programming styles used in the architecture body can be reduced in the range of synthesizable VHDL to a few basic shapes. Sometimes the use of certain VHDL styles is also set in the context of specific development projects:

Differences and similarities to traditional programming languages

In a hardware description language, the construction of a physical circuit is described model. Unlike most known programming languages ​​that define a sequential operation of individual instructions (usually on a single processor ) executed by a process of the operating system, VHDL hardware modules describes that are simultaneously existent and work simultaneously.

In VHDL, a distinction

  • Entities ( ' entity '), describe the individual circuit blocks with their inputs and outputs, and
  • Components ( ' component '), the instances of the entities represent (see class and object in object-oriented programming languages), and
  • Processes ( 'process' ) that summarize the parallel instructions.

Data are defined in VHDL in various types, often mimic the real circuit conditions, as well as integer operands. For processing, there are signals, variables, and constants.

  • Signals are used as inputs and outputs as well as for data transmission between concurrent processes on the same component. In a clocked circuit, a signal is used also for the storage of values. This is modeled in the case of synthesis as registers.
  • Variables are used within processes and serve there for the clear outline and simplify the code. A variable ( sequentially seen ) in a timed process read before it is written as a register is implicitly created in the synthesis.
  • Constants provide physically represents a hard wiring, in the simulation, they are synonymous with constants of traditional programming languages ​​.

The functional difference between signals and variables of the further fact that signals assume their new condition only at the end of a sequential process, while variables a behavior similar to programming languages, show and work assignments directly. This fact is especially for beginners usually confusing, but is clear once it has been internalized that a process is not a sequential series of commands, but everything happens simultaneously.

VHDL for analog circuits, VHDL -AMS

Since 1999, run as part of the IEEE different aspirations, future use VHDL for simulation and synthesis of analog and mixed-signal circuits. The term for this extended language is VHDL -AMS and it is in the standard IEEE 1076.1-1999 defined.

Under VHDL-AMS analog temperature sensors can be modeled, for example, with their electrical signal response as a function of the temperature at the connection terminals. It is also possible to model differential equations for the description of electrical network elements such as coils or capacitors in VHDL -AMS.

Currently, however, no synthesis tools are available for circuits described in VHDL -AMS. Only for the circuit simulation, various commercial software packages such as Saber of Synopsys, Mentor Graphics or AdvanceMS SMASH from Dolphin Integration on the market are already available. These simulation programs are in addition to the established analog circuit simulation programs SPICE -Class ( Eldo, Spectre, Hspice, etc.) to see. They allow the joint simulation of behavioral models with circuits on component level (Spice ). This is a basic requirement for the top-down method in circuit design. Since VHDL -AMS is a superset of VHDL simulation together with purely digital circuit parts in VHDL is also possible.

VHDL editors

  • HDL Designer is a commercial graphical input tool for VHDL and Verilog.
  • Crimson Editor for Windows
  • Data Flow: graphical input on UNIX
  • ZamiaCAD: open-source plugin for Eclipse
  • Signs: Plugin for Eclipse
  • Sigasi: Eclipse - based editor for VHDL and Verilog for Windows x86/x64, Linux x86/x64, Mac

Furthermore, there are many popular text editors add-on packages for VHDL support, for example, vi, Notepad and Emacs.

Also includes a VHDL editor with text highlighting and the like is available in standard VHDL simulators. This not only allows the entry of the code but also helps its integration and troubleshooting, as for example codes from the compiler / simulator / ... You can jump from error messages out and breakpoints in the source code are implemented.

VHDL simulators

  • ModelSim from Mentor Graphics, for Windows, Linux and Unix
  • ActiveHDL Aldec for Windows
  • RivieraPro Aldec, for Windows and Linux
  • Portunus of Adapted Solutions for Windows
  • SIMPLORER from Ansoft for Windows
  • SMASH from Dolphin Integration for Windows, Linux and Unix
  • ISE Simulator ( ISim ) from Xilinx, including free Wi- ISE WebPACK, for Windows and Linux
  • Quartus II from Altera, also free Web Edition, for Windows and Linux
  • GHDL for Windows and Linux
  • System Vision Mentor Graphics for Windows
  • NCSIM of Cadence Design Systems, for SunOS and Linux
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