VIA C3

  • Samuel 2 ( C5B )
  • Ezra ( C5C )
  • Ezra -T ( C5N )
  • Nehemiah ( C5XL )
  • Nehemiah ( C5P )

C3 (formerly VIA Cyrix III called ) The VIA is a x86 processor for Socket 370 VIA Technologies. Were developed, the CPUs of Centaur Technology, a subsidiary of VIA Technologies. The C3 series is the successor of WinChip CPUs from IDT. Centaur CPUs are developed with the focus on the best possible production costs. To make this possible, it is necessary to keep the area as small as possible. This had the inevitable consequence that the architecture had to be kept very simple. The C3 CPUs were therefore no performance miracles, but shined by a very low power consumption and low heat generation and by barely existing bugs. The CPU cores also come partly in the Eden series in the models Eden and Eden ESP -N used.

  • 2.1 Samuel
  • 2.2 Samuel 2
  • 2.3 Ezra
  • 2.4 Ezra - T
  • 2.5 Nehemiah
  • Nehemiah 2.6

Models

Samuel 2 ( C5B )

Already in mid- 2000, the Centaur Samuel ( C5A ) and VIA Cyrix III was brought to the market in early 2001 and then followed with the Samuel 2 now VIA C3 variant called with an on - the L2 cache of 64 KB. This additional cache was possible because you could reduce the structure size by a shrink to 0.15 micron.

Ezra ( C5C )

The Ezra is nothing more than a further shrink the Samuel / Samuel 2 now on 0.13 micron. The Ezra was the first CPU that was mass-produced in 0.13 micron. The smaller this time, the surface was not used to enhance the cache.

Ezra -T ( C5N )

Ezra -T is just a modified version of Ezra and allowed the use of the modified by Intel for the Tualatin bus protocol and can only be seen as Kompatiblitätsmaßnahme. The Ezra was completely replaced by the Ezra -T.

Nehemiah ( C5XL )

As the first significant revision came in early 2003, the Nehemiah on the market. Centaur boosted by this CPU, the speed of the FPU dramatically and made it so competitive. In addition, 3DNow was! replaced by SSE, which is better supported by software. Centaur has completely revised the CPU so that finally 100 % Binärkompatiblität the Intel Pentium Pro and thus also to the Pentium II, Pentium III and Pentium 4 could be achieved. Previously, it was necessary to compile software for C3 CPUs for Pentium architecture because the C3 uncontrolled introduced with the i686 family of standards of cmov instructions. cmov ( conditional move, is to avoid jumps ), although was perhaps the most important innovation in the i686 standard, but was nevertheless an optional part of the specification, i686. Formally, the C3 was therefore i686 - compatible. In practice, however, made ​​no difference between compiler " i686 with cmov " and " i686 without cmov ", so that did not run for i686 compiled programs on the C3.

As a special Centaur also built a one hardware random-number generator ( RNG), ie a random number generator, which is very useful for cryptographic applications. Because of these extensive changes ( even if one can speak of any new architecture), it was assumed that in the run-up to the fact that the Nehemiah would not come as C3, C4 rather than on the market.

Nehemiah ( C5P )

The Nehemiah is in the old tradition, only a revised Nehemiah, were incorporated into the still advanced encryption techniques. It is also used as a processing core in VIA Core Fusion platform.

Model data

Samuel

  • Codename: C5A

VIA Cyrix III See Article

2 Samuel

  • Codename: C5B
  • L1 - Cache: 64 64 KB ( data instructions )
  • L2 - Cache: 64 KB with processor clock
  • MMX, 3DNow!, LongHaul!
  • Side Socket 370, GTL with 100 and 133 MHz front bus
  • Operation voltage ( Vcore ): 1.60 V
  • Power consumption ( TDP): 6 W
  • Release Date: March, 2001
  • Manufacturing Technology: 0.15 micron TSMC
  • The size: 52 mm ² 15.2 million transistors
  • Clock rates: 700 to 800 MHz

Ezra

  • Codename: C5C
  • L1 - Cache: 64 64 KB ( data instructions )
  • L2 - Cache: 64 KB with processor clock
  • MMX, 3DNow!, Power Saver 3.0
  • Side Socket 370, GTL with 100 and 133 MHz front bus
  • Operation voltage ( Vcore ): 1.35 V
  • Power consumption ( TDP): 6 W
  • Release Date: June, 2001
  • Manufacturing Technology: 0.13 micron TSMC
  • The size: 52 mm ² 15.4 million transistors
  • Clock rates: 800, 866 and 933 MHz

Ezra - T

  • Codename: C5N
  • L1 - Cache: 64 64 KB ( data instructions )
  • L2 - Cache: 64 KB with processor clock
  • MMX, 3DNow!, Power Saver 3.0
  • Side Socket 370, AGTL with 100 and 133 MHz front bus
  • Operation voltage ( Vcore ): 1.35 V to 1.45 V
  • Power consumption ( TDP): 12 W
  • Date of publication:
  • Manufacturing Technology: 0.13 micron TSMC
  • The size: 56 mm ² at 15.5 million transistors
  • Clock rates: 800, 866, 933 and 1000 MHz

Nehemiah

  • Codename: C5XL
  • L1 - Cache: 64 64 KB ( data instructions )
  • L2 - Cache: 64 KB with processor clock
  • MMX, SSE, Power Saver 3.0, PadLock Engine ( 1x RNG)
  • Side Socket 370, AGTL with 100 and 133 MHz front bus
  • Operation voltage ( Vcore ): 1.40 V
  • Power consumption ( TDP): 15 W to 18 W
  • Release Date: January 22, 2003
  • Manufacturing Technology: 0.13 micron TSMC
  • The size: 52 mm ² at 20.5 million transistors
  • Clock speeds: 1,000, 1,066, 1,133 and 1,200 MHz

Nehemiah

  • Codename: C5P
  • L1 - Cache: 64 64 KB ( data instructions )
  • L2 - Cache: 64 KB with processor clock
  • MMX, SSE, Power Saver 3.0, PadLock Engine ( RNG 2x, 1x ACE), SMP
  • Side Socket 370, AGTL with 100 and 133 MHz front bus
  • Operation voltage ( Vcore ): 1.25V
  • Power consumption ( TDP): 12 W to 15 W
  • Date of publication:
  • Manufacturing Technology: 0.13 micron TSMC
  • The size: 47 mm ² at 20.4 million transistors
  • Clock speeds: 1,000, 1,133 and 1,200 MHz
Instruction set Microarchitecture Integrated Device Technology Cache (computing) VIA CoreFusion List of microprocessors VIA C7
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