VIA CoreFusion

VIA Core Fusion Processor Platform is a term of VIA Technologies for a combination of CPU and Northbridge. The main processor this is an x86 -compatible processor core of Centaur Technology for use.

  • 2.1 Mark
  • 2.2 Luke

Development

Although already at CeBIT 2003 for the first time the Core Fusion concept was announced, it took until 2005 before the first products were available. The Core Fusion platform currently consists of two products, but should be supplemented in the near future to a third product.

Marrow

VIA Mark Core Fusion is the smallest model and combines a VIA C3 processor ( Nehemiah processor core ) with a VIA Apollo PLE133T Northbridge. This combination results in the support of PC133 SDRAM and an ISA bus ( on the VT82C686B South Bridge ). This ISA bus is mainly used for industrial applications where specific measurement cards and the like are used is important. The graphics capability is due to the older Twister - T graphics solution but rather below average. So especially 2D skills such as hardware accelerated rotation of the screen output are not supported.

Hatch

This shortcoming was largely remedied VIA Luke CoreFusion. Its integrated VIA CN400 North Bridge VIA UniChrome Pro graphics core has much more sophisticated graphics capabilities. A main processor to be the core of the processor Nehemiah VIA C3 is used. However, in this Core Fusion variant, owing to the new southbridge connection to the ISA bus can be waived: instead of the PCI bus now comes V-Link is used, which is a VIA South Bridge makes necessary from the VT8231, the more no ISA support offer. However, DDR SDRAM is now up to DDR/400 used.

John

As a third variant VIA John Core Fusion is planned. In this variant of Esther processor core of the VIA C7 with a matching Northbridge with Chrome9 HC graphics core is to be combined. This means that both a support for DDR2 SDRAM and 3D functions on DirectX 9.0c level and extended support for video acceleration ( Chromotion engine) will be available.

Model data

Marrow

  • Processor core: Centaur Nehemiah L1 - Cache: 64 64 KB ( data instructions )
  • L2 - Cache: 64 KB with processor clock
  • MMX, SSE, Power Saver 3.0, PadLock Engine ( RNG 2x, 1x ACE), SMP
  • AGTL 133 MHz Front Side Bus
  • Storage controller: SDRAM with max. 133 MHz ( PC133 )
  • Twister integrated graphics core T
  • 82C686B VIA South Bridge (connection via PCI bus )
  • Power consumption ( TDP): 6 W and 8 W
  • Date of publication:
  • Manufacturing Technology:
  • Package: HSBGA, 42 x 57 mm
  • Clock speeds: 533 and 800 MHz

Hatch

  • Processor core: Centaur Nehemiah L1 - Cache: 64 64 KB ( data instructions )
  • L2 - Cache: 64 KB with processor clock
  • MMX, SSE, Power Saver 3.0, PadLock Engine ( RNG 2x, 1x ACE), SMP
  • AGTL 133 MHz Front Side Bus
  • Storage controller: DDR - SDRAM with max. 200 MHz ( PC3200 )
  • Integrated UniChrome Pro graphics core
  • VIA VT8231 South Bridge from (connection via V-Link)
  • Power consumption ( TDP): 6 W, 8 W and 10 W
  • Date of publication:
  • Manufacturing Technology:
  • Package: HSBGA, 37 x 53 mm
  • Clock rates: 533, 800 and 1000 MHz
Northbridge (computing) Industry Standard Architecture S3 Savage S3 Chrome DDR-SDRAM List of microprocessors WinChip
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