X86 is the abbreviation of a microprocessor architecture and the associated instruction sets, which are designed, inter alia, the chip manufacturers Intel and AMD.

The x86 architecture is named after the processors of 8086/8088-Reihe, with which it was introduced in 1978. The first follow- processors were later named with 80186, 80286 and so on. Due to the impossibility digit combinations protect trademark law, went Intel and most competitors after the introduction of the Intel 80486 to on to use the word marks such as Pentium or Celeron, but the old numbering scheme was retained as the name of the whole family. Intel itself is called the IA-32 architecture today as an abbreviation for " Intel Architecture with 32 -bit. "

  • 2.1 Real Mode
  • 2.2 Protected and Enhanced Mode 2.2.1 register


The x86 architecture in 1978 with Intel's first 16 -bit CPU, the 8086, introduced which was intended to replace the older 8 -bit processors 8080 and 8085. Although the 8086 was initially not very successful, in 1981, IBM introduced the first PC from which a scaled-down version of the 8086, the 8088, as the CPU used. Due to the enormous success of the IBM PC and its many clones, the so-called IBM -compatible PCs, the x86 architecture has been within a few years one of the most successful CPU architectures in the world and has remained so to this day.

Except Intel and other manufacturers have produced over the years x86 - compatible CPUs, including Cyrix (now VIA Technologies), NEC, UMC, Harris, TI, IBM, IDT and Transmeta. The largest manufacturer after Intel x86-compatible processors was and is the company AMD, which has now become next to Intel becoming a driving force in developing the x86 standards.

Intel developed the 8086 1978 at the time of coming to an end 8- bit era. With the 80386, Intel introduced then already in 1985 the first x86 CPU with a 32- bit architecture. Today, this architecture is known as the IA -32, often also referred to i386 architecture; it is so to speak the extension of instruction sets of 8086 and 80 286 to 32 bits, which includes instruction sets but complete with a. The 32- bit era was the longest and most lucrative segment of the x86 history, with IA -32 - largely under the leadership Intel - permanently further developed. Only in 2003 broke for x86 64- bit era, this time at the initiative of AMD. The 64 bit x86 Standard called AMD64 and was taken under the name Intel 64 Intel.

The IA -64 architecture used by Intel in the Itanium product line has nothing to do with IA -32. It is a new development which does not contain any traces of x86 technology except a x86 emulation (only in the oldest Itanium series).

List of x86 generations


The x86 architecture uses a CISC instruction set with variable instruction length. Memory accesses in word size are allowed on non- word - aligned memory addresses. Words are stored in little-endian direction. Easy portability of Intel 8085 assembler code was a driving force behind the development of architecture. This required some non-optimal and problematic in hindsight design decisions.

Today's x86 processors are hybrid CISC / RISC processors, because they translate the x86 instruction set first in RISC micro-instructions of constant length, can be applied to the modern micro - architectural optimizations. The transfer is first to so-called reservation stations, that is to small buffers that are upstream of the different arithmetic units. The first hybrid x86 processor was the Pentium Pro.

Real fashion

Intel 8086 and 8088 had 14 16 -bit registers. Four of them (AX, BX, CX, DX) were general-purpose registers. In addition, each had a special function:

  • AX (English accumulator register) served as a preferred destination for arithmetic operations
  • BX (English base register) served to address the starting address of a data structure
  • CX (English count register) served as a counter for loops (loop instruction ) and move operations
  • DX ( engl. data register) served as data registers for the second operand.

On each register could by two separate bytes are accessed ( the high byte in BX under the name bra, the low byte as BL). Of the two pointer registers shows SP ( " stack pointer " ) on the top element of the stack and BP ( " base pointer " ) can refer to another place in the stack or memory show (often BP is a function used as a frame pointer ). The two index registers SI ( "Source Index") and DI ( "Destination Index") can be used as an index into an array for block operations or together with SP or BP. In addition, there are the four segment registers CS ( " code segment " ), DS ( " Data Segment " ), SS ( "stack segment " ) and ES ( "Extra segment " ), with each of which the base address is set for a 64 kB large memory segment. There is also the flag register, the flags such as carry, overflow, zero, etc. may be included, and the instruction pointer (IP) pointing to the current instruction.

In this scheme, different segment / offset pairs can point to the same physical address. If DS A111h and SI is 4567h, DS shows: SI also to the above address A5677h. The scheme should facilitate the portability of Intel 8085 code and an entire generation of programmers has a headache.

In addition, the i8086 had 64 kB of 8-Bit-I/O-Adressraum (alternatively 32 kB with 16-bit) as well as a hardware-supported stack of also 64 kB. Only words (2 bytes ) can be stored on the stack. The stack grows towards lower addresses and SS: SP points to the last placed on the stack word ( the lowest address ). There are 256 interrupt may be triggered by hardware or software. The interrupts can cascade and use the stack to store the return address.

Protected and Enhanced Mode

The Intel 80286 processor knew another operating mode, the "Protected Mode". By integrating a MMU (English " Memory Management Unit " for memory management unit ) on the chip could be addressed in protected mode up to 16 MB of memory. A special MMU registers pointing to a segment table in main memory, in which the 24 -bit base addresses of the segments were defined. The segment registers were then used only as an index into this segment table. In addition, each segment could be assigned to one of four privilege levels ( " rings " called ). Overall, these changes meant an improvement. However, the software was incompatible for the protected mode with the real mode of the i8086 processor.

The Intel 80386 probably brought the biggest jump for the x86 architecture. With the exception of the chip "Intel 80386SX " which supported only 24 -bit addressing and had a 16- bit data bus, were all 386 fully 32- bit - registers, instructions, I / O space and memory. Up to 4 GB of memory could be addressed. For this, the Protected Mode became " 32 -bit enhanced mode " extended. As on the 80286 the segment registers were used as an index into a segment table that described the allocation of memory in Enhanced Mode. However, 32- bit offset could be used in each segment. This led to the so-called "flat memory model " in which each process only a 4 GB data segment and a 4 GB code segment is provided. Both segments start from address 0 and 4 GB in size. The actual memory management is performed only by the also introduced with the 80386 paging, a mechanism that divides the whole memory into equal parts (English pages, so pages of memory ) and per process allows an arbitrary mapping between logical and physical addresses what the realization of virtual memory greatly simplified. We have added no new general-purpose registers. However, except for the segment register all registers have been broadened to 32 bits. The extended registers AX called henceforth the EAX, from SI ESI etc. Two new segment registers called FS and GS were added yet.

The basic architecture of the 386 - processor (also called IA -32) was the basis of all further developments in the x86 architecture. To date, all x86-compatible CPUs operate on the principle of i80386.

The hitherto separate math coprocessor 80387 was from the next CPU, the "Intel 80486 ", integrated directly into the processor ( with the exception of the 486SX, which has no coprocessor ). With this floating-point co-processor could be implemented in hardware. Without him, they had to be mapped to calculations with whole numbers (emulation ). Not only are quite many instructions per floating point operation requires, also occur frequently in loops and branches, so that floating-point operations were performed comparatively very slowly without the coprocessor.


  • AX / EAX / RAX: Accumulator
  • BX / EBX / RBX: Base
  • CX / ECX / RCX: counter
  • DX / EDX / RDX: data / general purpose
  • SI / ESI / RSI: swelling index ( strings)
  • DI / EDI / RDI: destination index (strings )
  • SP / ESP / RSP: stack pointer
  • BP / EBP / RBP: stack segment ( start address)
  • IP / EIP / RIP: instruction pointer

MMX and 3DNow!

In 1996, Intel 's MMX technology (English Matrix Math Extensions, especially from marketing but also frequently Multi- Media Extensions dubs ). MMX defined eight new SIMD registers of 64 bits width, however, used the same space as the Register of Floating Point Unit ( FPU). While this improved the compatibility with existing operating systems, still had to back up only the familiar FPU registers when switching between different applications. But had to be switched between MMX and FPU -consuming. On top of that MMX was limited to integer operations and a long time was not properly supported by the compilers. In particular, Microsoft struggled to equip the house with at least compiler support for MMX intrinsics. MMX was therefore only relatively rarely used, most likely even for 2D video editing, image editing, video playback, etc.

1997 Advanced AMD MMX instruction set for floating point operations for single precision floating point and called the resulting technology 3DNow!. While this did not solve the compiler problems, but 3DNow! could only be used for 3D games that rely on fast floating point operations, in contrast to MMX. Games developer and manufacturer of 3D graphics programs used 3DNow!, To improve application performance on AMD's K6 and Athlon processors.

Streaming SIMD Extensions

In 1999, Intel with the Pentium III processor the SSE instruction set. How AMD Intel added mainly added floating-point SIMD instructions. Furthermore, we created a separate function for SSE unit on the processor with 8 new 128 -bit registers ( XMM0 to XMM7 ), which no longer superimposed with the floating point registers. However, since these new registers must be saved even when a context switch from the operating system, a lock on the CPU was installed, which must be unlocked only by SSE - enabled operating systems to make the SSE registers available in application programs.

AMD processors initially supported only 64- bit instructions of the extension, which operate in the MMX functional unit, as separate functional unit was missing completely. A majority of these commands works only with data of type integer, so there is also the name ISSE, where I stands for integer. From the Athlon XP processor SSE is fully supported.

SSE2, introduced by Intel in 2001 with the Pentium 4, added first be more integer instructions to the SSE registers and second 64 -bit SIMD floating-point instructions. The former made ​​MMX almost obsolete, and the latter also allowed for conventional compilers to use SIMD instructions. Therefore, AMD chose with the introduction of the 64 -bit SSE2 as an integral part of the AMD64 architecture, so all 64 -bit x86 processors support this extension ( AMD Athlon64 processors starting ).

With the Prescott revision of the Pentium 4 Intel gave out from 2004 SSE3, which mainly provides memory management and thread management instructions to boost the performance of Intel's Hyper- Threading Technology.

AMD has been dominating the Athlon 64 processors with the nuclei Venice and San Diego also the SSE3 instruction set.

64 bit

Around the year 2002, the memory expansion of modern x86 machines reached the caused by the 32 -bit address size addressing limit of the x86 instruction set architecture of 4 GB. Although Intel had already introduced with the Pentium Pro is a possibility to address more than 4 GB of RAM, but its use was programmatically consuming and the per process usable memory remained so still limited to 4 GB.

Intel originally wanted to perform the jump to 64 bit with a new processor architecture called IA -64, but could this be developed only as a niche product in the market segment of servers and workstations. AMD, however, extended the 32-bit processor architecture to 64 bits and called this extension AMD64. Later, Intel took over large parts of this extension under the name EM64T, then finally under the commonly used today for Intel products name Intel 64

For 64 -bit processors, which will be based on the x86 architecture, the term x86 -64 or x64 used briefly.


Although the virtualization of a x86 processor is complex due to the comprehensive architecture, there are several products that provide a virtual x86 processor available, including VMware, Hyper- V and Virtual PC, or even open source software such as Xen or VirtualBox. Hardware -side virtualization is also available as an extension, it will be at Intel "Intel VT" ( for Virtualization Technology ), called in AMD " AMD Virtualization ".



X86 - compatible processors have been developed and manufactured by many companies, including: