Zilog Z180

Zilog Z180 is an 8 -bit microprocessor, which has been developed in 1985 under the name of Hitachi HD64180. Later the company Zilog Inc. built the chip almost unchanged under the name Z180.

Command structure

The Z180 has a processor core that is fully code - compatible to the Z80. First came here the microcode technology with execution pipelining is used. Some commands require less machine cycles than the original Z80. A special interrupt Reserved Instruction Trap is triggered when an invalid instruction is detected. The popular Z80 with some programmers undocumented instructions are so taboo for the Z180. New additions include special instructions for addressing the internal registers and a multiply instruction.

Periphery

The success of the Z180 is mainly due to the fact that a number of peripheral devices are integrated on the chip. These are as follows:

  • Clock generator. Only a crystal and two capacitors are required.
  • Memory management memory management unit ( MMU ) for 1 MB of RAM.
  • Two DMA controller with memory storage and memory IO - Transfers. The DMA controllers support the full 1 Mbyte address space.
  • Programmable wait state generator, separately for memory and IO accesses.
  • Programmable DRAM Refreh controller.
  • Two asynchronous serial full-duplex interfaces ( UART) with programmable baud rate generator for transmission rates 300-38400 baud and support of modem control lines.
  • A pulsed, high-speed serial interface for the construction of multi-processor systems.
  • Two 16-bit programmable timer (timer).
  • Two external universal interrupt inputs.

Memory management

Since the Z80 is capable of addressing up to 64 Kbytes logically, the MMU manages memory via so-called memory banks. There are three different areas:

  • Common Area 0
  • Bank Area
  • Common Area 1

The MMU hide the physical memory in 4 kbyte blocks in the logical address space. Common area 0 and 1 are both at the lower and upper end of the logical address space, and are usually associated with fixed physical storage areas. In the intervening banking ( Bank Area), the program may, if necessary switch the mapping of logical memory.

Housing types

  • 64-pin DIP package
  • 68-pin PLCC
  • 80-pin QFP
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