Adi Shamir

Adi Shamir (Hebrew עדי שמיר; born July 6, 1952 in Tel-Aviv) is an Israeli cryptology expert. Along with Ron Rivest and Leonard Adleman, he is one of the inventors of the RSA cryptosystem.

Life

Adi Shamir received his Bachelor of Science at the University of Tel Aviv in 1973, In 1975 the Master of Science degree and a doctorate in 1977 at the Weizmann Institute of Science. His doctoral thesis was titled Fixed Points of Recursive Programs. After a year of postdoctoral work at the University of Warwick, he conducted research from 1977 to 1980 at MIT. He then returned as a professor back to the Weizmann Institute, where he works to this day. He is also a visiting professor at the École Normale Supérieure in Paris.

In 1979 he showed that a natural number N with proportional to log N many computational steps can be factored if the intermediate results in registers are determined with unlimited bit length. In the same year he developed Shamir 's secret sharing, a method, a secret to multiple instances ( privy ) to share, with a certain subset of these instances is required to reconstruct the secret. Named after him is also the Fiat -Shamir protocol from the year 1986. Together with Eli Biham, he developed the technique of differential cryptanalysis in 1990. A research result of the 1992 is the exact characterization of the relationship between interactive proof systems (IP ) and the complexity class PSPACE. At Eurocrypt Conference 1994 Shamir provided with Moni Naor against another secret sharing method, the visual cryptography.

In recognition of their contributions for cryptography Rivest, Shamir and Adleman received the Turing Award for 2002. In 1983 he received the Erdős Prize, and in 2008 he was awarded the Israel Prize. In 1996 he received the Paris Kanellakis Award.

Along with Scott Fluhrer and Itsik Mantin he RC4, which is also used in the Wired Equivalent Privacy - system, successfully attacked. Together with Claus -Peter Schnorr, he developed in 1986 a parallel algorithm for sorting on a two-dimensional processor array with the term.