AMD K5
- Base 5
- Socket 7
- SSA / 5 (Model 0)
- 5k86 ( Model 1 )
The AMD K5 is an x86 microprocessor company AMD and the first complete personal development of AMD. He competed with the Intel Pentium, Cyrix 6x86 NexGen Nx586 and.
- SSA 3.1 / 5 (Model 0)
- 3.2 5k86 ( Model 1 )
Background
After AMD had previously copied minimal change in the years especially Intel's microprocessor developments, the manufacturer had to reorient and seek its own development department and processor architecture after several disputes with Intel. The K5 was the first result of this change in orientation, however, was fraught with problems, making the K5 was late deal on the market. Successor was the AMD K6, which, however, was not based on the K5, but on the NexGen Nx686.
Technology
Models
AMD had problems in the development time and the manufacturing yield, so that the K5 came on the market a year later than originally planned. This version was still a kind of " pre-release ", known as SSA / 5, with errors in the L1 cache and the branch prediction. It was first described as 5k86, and later sold as K5. The corrected version, referred to as 5k86, was sold only as K5. The SSA/5-Reihe the K5 included models from 75 to 100 MHz ( 5k86 P75 to P100, later K5 PR75 to PR100 ); 5k86 processors came with clock frequencies of 90 MHz to 133 MHz ( K5 PR120 PR200 up ) on the market.
Architecture
The K5 is a x86 - decoding unit that breaks down (based on the Am29000 RISC family) all x86 instructions for execution on RISC instructions internally a RISC processor. This principle is used in the meantime with all modern x86 CPUs.
K5 has five integer units, which are designed as an out - of-order pipeline and a non- pipelined FPU ( Intel Pentium has two designed as in-order pipeline integer units, and a pipelined FPU). Register renaming and speculative execution to improve the parallel execution ability of the pipelines or reduce their blockade. The buffer for the branch prediction is four times greater than that of the Pentium (where the branch prediction works even not better) and the L1 cache is twice as large ( and four times instead of two way set associative ). These improvements allow the K5 a higher integer performance than an identically clocked Pentium. For this reason, AMD used the already known from the Am5x86 P rating to indicate the performance relative to Pentium. For floating-point calculations by the FPU an AMD K5 works but slower than a Pentium with a clock frequency corresponding the P rating.
Model data
SSA / 5 (Model 0)
- Product name: 5k86 P75/P90/P100; later K5 PR75/PR90/PR100
- L1 cache: 8 16 KB ( data instructions )
- Socket 5 and Socket 7 with 50, 60 and 66 MHz Front Side Bus
- Operation voltage ( Vcore ): 3.52 V
- Release Date: March 27, 1996
- Manufacturing Technology: 0.50 micron and 0.35 micron
- The size: 251 mm ² ( 0.50 microns ) and 161 mm ² (0.35 microns ) at 4.3 million transistors
- Clock rates (power ): 5k86 P75, K5 PR75: 75 MHz ( 11.63 W)
- 5k86 P90, K5 PR90: 90 MHz ( 13.96 W)
- 5k86 P100, K5 PR100: 100 MHz ( 15.51 W)
5k86 ( Model 1 )
- Product name: K5 PR120/PR133/PR150/PR166
- L1 cache: 8 16 KB ( data instructions )
- Socket 5 and Socket 7 Side with 60 and 66 MHz front bus
- Operation voltage ( Vcore ): 3.52 V
- Release Date: October 7, 1996
- Manufacturing Technology: 0.35 micron
- The size: 181 mm ² (0.35 microns ) at 4.3 million transistors
- Clock rates (power ): PR120: 90 MHz ( 12.37 W)
- PR133: 100 MHz (13.75 W)
- PR150: 105 MHz
- PR166: 116.6 MHz ( 16.04 W)
- PR200: 133 MHz ( it was originally planned, a sale was no longer held )