Address decoder

In microelectronics, computer architecture and technical computer science, an address decoder evaluates ( engl. address decoder ) the bits of a current address in order to select the associated memory cell or a particular part of the memory ( Speicher-Modul/Speicher-Chip ).

An address decoder can be realized technically by a combinational circuit (also switching power ). It can be described in its function by Boolean algebra.

Address decoder selects the memory cell in a memory of

An address decoder is a component commonly used in the microelectronics industry, which is used for selecting memory cells in randomly addressable storage modules.

Such a memory cell is composed of a fixed number of memory elements or bits. The address decoder is connected to an address bus and reads out the address applied there. A special switching logic it calculates from this address to be accessed which memory cell. He then selects that cell, by selecting it through a dedicated control line. This line is referred to as select line. In dynamic memories (DRAM) are available from the memory array row and column select lines, which are controlled by on-chip address decoder.

According to which logic is used to select the memory cell, can - depending on the type of decoders - be programmable under certain circumstances.

Address decoder selects the appropriate memory module from

An address decoder is also used to choose the appropriate of a plurality of memory modules or storage chips, when a specific address is supplied from the address bus of the processor system.

For this purpose, the memory modules or memory chips have selection inputs, mostly as a chip select pin ( CS) or chip enable pin (CE) pin called. Often these inputs a negative logic function (CS or CE) have, ie with an applied logic zero ( low voltage level ) is selected.

By the respective different combinational logic of the address decoder places the memory modules or chips in the address space of a processor. Often, the memory modules have a lower capacity than the address space. It can usually several - also completely similar structure - modules are used. It must be ensured that they differ in Addessbereich.

Uniqueness or ambiguity in the mapping address and memory cell

Access to these modules is determined by the address decoder usually clearly organized ( injectivity ). That an address leading to a memory cell in a module. It does not result in memory cells in a plurality of modules, or a plurality of memory cells in a module.

In a reversal unambiguous assignment ( one correspondence, bijective ) between address and cell in the module is sometimes omitted because of the effort of many input lines in the address decoder. Thus, the address is decoded only incomplete. Thus, a memory cell associated with multiple addresses. As a memory module is in several areas of the address space. This phenomenon is often referred to as a mirror addresses or mirrored modules and also called "Mirror". The incomplete decoding can sometimes save hardware costs, but occasionally causes complications for the software.

Example of a 8-bit microprocessor

The frequently used address width of 16 bits in 8- bit microprocessors corresponds to an address space with 64k capacity. Addresses are almost always in hexadecimal notation, here - as in the C programming language - is the "0x" prefix are used as indicator. The address space of the 8-bit microprocessor, the addresses from 0x0000 to 0xFFFF.

The address lines are designated to. The data bus is 8 bits wide.

The address space is completely filled in the example with 4 pieces identical RAM chips 16k x 8. The name 16k x 8 means 16 k capacity with the word length of 8 bits.

To this end, four address decoder can be realized, which form their outputs CSn as combinatorial logic functions of the address lines of the address bus.

There should be evaluated in this example, the most significant address lines A15 and A14. The remaining 14 address lines can be directly fed to the RAM chips. For the following functions for the signal CS each RAM chips would be available:

Selection for the first RAM chip

Selection for the second RAM chip

Selection for the third RAM chip

Selection for the fourth RAM chip

With the above address decoders so placed as follows: