Clock skew

The clock skew (clock skew ) is a phenomenon of synchronous circuits and synchronous data transfer process. It describes the time difference between the arrival of a clock edge of the first element to be considered (for example, a flip-flop ), and the time of arrival of a second element.

Depending on the selection the clock skew can take positive or negative values, the maximum absolute difference describes a limit on the upper frequency. Ideally, the timing offset is zero, which is not physically feasible. In real synchronous circuits, the amount of clock skew, depending on the technology in the range of some 10 ns and can be reduced by special measures to some picoseconds. To minimize the clock signal is distributed to the synchronous digital circuits in their own clock distribution network which may be constructed in the structure as an H - Tree. Other options provide delay-locked loops represent that allow a specific phase shift in the clock signal for specific circuit areas.

Occurrence in real circuits

The description is adjacent simplest synchronous circuit, which consists of two series-connected D flip-flops as memory elements. Each D flip-flop accepts a rising edge the state at its D input and outputs this value at its output Q. In an ideal circuit with no run times the first flip flop assumes the state of the D input line, the second clock edge of the second flip-flop.

In a real circuit, enter additional times, both by the flip-flops as well as along the different length leads to: The clock signal is shifted at the point CLKB at second flip-flop against the clock signal at point CLKA by the spatial extension of time - this time difference is called clock skew tc. Together with the terms of the flip-flop, shown in the timing diagram as an arrow, and the transit time along the data path, this represents a switching network, this may lead to the data signal Q at the output of only one clock period later changes, as if the term would be correspondingly shorter data path. This produces the following to be observed time problems of synchronous circuits that need to be avoided in circuit design through the choice of topology or clock frequency:

To avoid this time- error special tools are used for timing analysis in the development of the synchronous circuits that determine the propagation times by means of the known technology parameters of the semiconductor chip, and can identify possible dynamic state error in the actual circuit design in the net-list.