Double Data Rate

Double Data Rate (DDR, also: double pumped), in computer technology, a method which can be transmitted with the data on a data bus Double Data Rate.

Similar procedures are Quadruple Data Rate ( QDR ) with quadruple and Octal Data Rate ( ODR) at eight times the data rate.

Technology DDR

The data bits are transmitted on the rising and falling edge of the clock signal, rather than just in the ascending as in the conventional single data rate method. Thus, not the frequency of accesses must be doubled to the memory cells, use is made of the so-called ' Prefetch' technique: if an access will be removed from its storage box twice as much data as can be given at once to the outside. One half of the data is output at the rising clock edge, while the other half is stored temporarily and will be output at the falling edge. Thus leading to an acceleration, the number of contiguous requested data ( = " burst length " ) must always be equal to or greater than twice the bus width. Since this is not always the case, the data throughput of DDR SDRAM is not exactly twice as high compared to classical ( SDR ) SDRAM in the same clock frequency. Another reason is that the address and control signals, in contrast to the data signals provided with a clock edge.

Applications

The technique is used for example when connecting processors ( front side bus ), memory ( DDR SDRAM ), Mass Storage ( SCSI Ultra-160/Ultra-3 ) and graphics card (PCIe ).

Designations

In giving the clock frequencies of double data rate, the clock frequency of the bus connections is often confused with the data rate, such as a processor with 100 MHz clock frequency and double data rate is referred to as " 200 -MHz bus ." This is supported by the marketing name FSB200.

A name starting with a PC and then three digits are the bus speed in MHz (eg PC -133 or PC133 = 133 MHz). Four digits, however, describe the data transfer rate in MB / s, so has PC -2700 on an imaginary of 166 MHz DDR SDRAM memory module out. Calculation: 166 MHz * 2 ( since DDR) * 64 -bit ( bus width ) = 21248 MBit / s / 8 bits / byte = 2656 MB / s, rounded up 2700 MB / s The PC specifications are thus not limited to the DDR technology and only makes sense in conjunction with the specification of the bus and Technology designation ( with bus width and this factor is then clearly defined ).

Further developments: DDR2 and DDR3

DDR2 and DDR3 are further developments of this concept, especially for PC's memory, where instead of using dual - prefetch, working with four- or eight- prefetch to allow a higher clock rate of the I / O buffer. In DDR2, while the actual memory cells are operated at only half the cycle of the I / O buffer. The marketing Technically here often called four- prefetch arises on the one hand on the DDR process (× 2) and on the other about this Taktdopplung (× 2) - in total, a four - prefetch. In the DDR3 is increased apparently in that between the clock of the I / O buffer and the timing of the actual memory cells, a difference in height is there four times - along with the DDR process an eight- prefetch. Although the memory cells secrete the 90 % is significantly larger portion of the memory chips in the time signature of DDR2/DDR3-Speichern the clock of the I / O buffer is considered "official".

DDR2 memory chips used in DDR2 SDRAM in current motherboards many manufacturers and systems, DDR3 is the middle of 2007 came on the market. The often built on graphics cards GDDR3 memory technology build on DDR2 and not DDR3 as its name suggests.

Besides developments: GDDR2 and GDDR3

GDDR2 and GDDR3 are locations that are fitted exclusively on graphics cards. Contrary to what the name suggests, is based on GDDR2 and GDDR3 SDRAM DDR to DDR2 SDRAM. This is due to the fact that GDDR2 and GDDR3 are no official specifications, but represent just marketing names of major graphics chip developer.

Related developments: QDR II and QDR

Quad Data Rate RAM refers to a device which combines the advantages of DDR SDRAM and dual- port RAM. It has separate read and write ports can be read and written so as to independently of each other without collision. However, the data share a common address line. This can transmit simultaneously on rising and falling edge data, the QDR SRAM on both ports, resulting in a fourfold increase in the data rate, the bottom line. There are two types of QDR SRAM, the two -word burst, and the variant 4 -word burst variant. That is, during a read or write access is equal to 2 or 4 words are read or written. QDR found, for example at the system bus of the Pentium 4 using ODR at the AGP bus ( AGP 8X ) and XDR DRAM.

QDR II RAM is an improved variant of the QDR RAM with recirculated pulse outputs, so-called echo clocks that are used for synchronization. So that the window of valid data at the same frequency enlarged by up to 35 %. The latency time is longer by a half clock when compared to QDR SRAM, but generally can be run higher data rates, so that throughput increases.

• Data transfer rate
• Computer Architecture
• Abbreviation