Flip-flop (electronics)

A flip-flop (English flip-flop), often also referred to as flip-flop or bistable circuit is an electronic circuit that assume two stable states and therefore an amount of data of one bit can be stored for a long time. It is the basic building block of sequential circuits is an indispensable component of digital technology and thus a fundamental part of many electronic circuits of the quartz watch to the microprocessor. In particular, it is very common in certain embodiments of the computer memory chip ( static memory devices ) contain elemental 1 -bit memory.

• 4.1 RS flip-flop
• 4.2 D flip-flop
• 4.3 JK flip-flop
• 4.4 T flip-flop

• 8.1 Simple example of an elevator controller
• 8.2 Widely used in digital electronics

History

Was invented the flip-flop 1918 by the British William Henry Eccles and Frank W. Jordan on feedback radio tube amplifiers in search of counting circuits and received originally the name Eccles -Jordan circuit.

Characteristics

Flip-flops differ in the number and the logical function of its inputs (to be described by its characteristic equation), the time response to these input signals, and in particular, the clock signals (timing), the possibility of direct feedback of the output signals to the inputs (transparency or counting flip-flop ), and the structural design (master-slave - principle or not). However, common to all is that they have two stable states, which can be measured at an output. These states are " set " (set), and " reset " (reset) called. Between these states may be switched by signals on the inputs. Usually, in addition to the output Q, another Q output is available, against which the negated value of Q. The initial state ( ON state ) is not defined with a simple flip-flop consisting of two bipolar transistors (as shown in the illustration at right ). This can be done afterwards by an RC member on one of the two inputs.

A flip-flop is configured, for example, in transistor-transistor logic (TTL), then the state corresponding to " set " a voltage of 2.4 to 5 volts at the output Q. On the negated Q output will be 0 to 0.4 volts. With the use of a positive logic, this condition is referred to as Q = 1 and Q = 0 interpreted. " Reset " in the state of the values ​​are interchanged at the outputs of (Q = 0 and Q = 1).

The simple flip-flop is the unclocked RS flip-flop which has the two inputs S and R. The input S sets the output of flip-flop that is in the state " set " (S = set). The input R resets the output, sets the flip-flop that is in the state " reset " (R = reset ). The characteristics of the RS flip-flop and on the other flip-flop types are explained in more detail below.

Through the interconnection of several flip-flops create complex systems such as counters (asynchronous or synchronous), data memory ( semiconductor memory ) and microprocessors. Flip-flops are the basic building blocks for the entire digital technology and microelectronics of today, including the computer.

Classification on the basis of timing dependence

Not clocked flip-flops

The condition of the above-introduced unclocked SR flip-flop is directly determined by the level of the input signals S or R. Such flip-flops is called asynchronous level-triggered (level -triggered ) flip-flops. But there is also the possibility that a flip-flop changes its state only during a level change in the input signals and the level of the input signal itself has no further effect. Such flip-flops is called asynchronous edge-triggered ( edge triggered ) flip-flops. For the practical realization earlier differentiating elements were used. Today, the edges are usually transformed with the help of run-time differences in short spikes or they are evaluated directly by volatile internal states.

Clock -controlled flip-flops

Since the input signals are present only stable at certain intervals, it is often desired that a flip-flop responds only at certain times of the input signals. This behavior can be realized by using a clock signal, which activates the control inputs of the flip-flop at certain times. Consider a clock signal which allows synchrony with other circuit components and the formation of synchronous circuits. Here it is important to distinguish the manner in which a flip-flop clock signals taken into account. The following figure shows this regard, such as various flip-flop types depend on each other.

Clock -state and clock- edge-triggered flip-flops

Clock -controlled flip-flops are used in synchronous switching works as memory elements. They take their data and control signals synchronously by a single ( within the respective switching device ) clock signal and can be divided into clock-state and clock- controlled edge-triggered flip-flops.

• Simple clock-state- controlled flip-flops respond during the entire active clock phase to the input signals and extend their changes through the exit. Such transparent clock- level-controlled blocks are not directly feedback- capable and are mainly used in the English literature as a latch, ie pawl switch, called ( strictly speaking, only edge-triggered flip-flop blocks called ).
• Adopting the state of a transparent "master flip-flop " on the falling clock edge in a " slave flip-flop", the result is a feedback- enabled clock- Level-controlled " classical " master-slave flip-flop ( eg type 7472 ) used as the counter flip-flop can be used.
• Clock edge -controlled flip-flop can change state only while the clock edges. Thus, the flip-flop responds only after the clock edge for a very short time on the signals present at the inputs. In the remaining time, between the edges, the previously set condition is stored and does not change, as opposed to clock-state- triggered flip-flops, even when the input signals change. This clock edge-triggered flip-flops are in principle capable of feedback and can be used as counting flip-flop. One distinguishes front edge triggered ( change with increasing (positive ) clock edge ), back edge-triggered ( change on falling (negative ) clock edge ) and two edge-triggered ( acquisition with increasing, with output falling clock edge ) flip-flops.
• Two Edge-triggered flip-flops are often implemented as a "master-slave flip-flop". They consist of two series-connected flip-flops. The rising edge resets only the front edge triggered master, the falling takes over the state to the slave. Only this is routed to the outside, so that the output reacts only with the falling edge. Since ( real ) two edge-triggered flip-flops are but to realize very complex, they are rarely used in practice.

Flip-flop types

The following are some typical flip-flop is presented. They differ mainly by their logical behavior, ie the influence of the current state and the values ​​of the currently applied input signals ( data and control signals) to the subsequent state. This influence is described by the characteristic equation of the flip-flop. This describes the external flip-flop behavior and therefore abstracts the type of timing. It is usually in the form of a truth table (also switching sequence or machine table called ) led to the specification of the flip-flops.

RS flip-flop

An RS flip-flop ( reset-set flip-flop ) is the simplest type of flip-flops. Basic element of these circuits is a flip-flop without a clock control, as shown in the following table in the first row. With appropriate additional circuitry can be generated from both level-clocked RS flip-flop ( asynchronous ) circuits and clock edge-triggered RS flip-flop. This RS flip-flop circuits used as a reason for building more complex flip-flops.

An RS flip-flop has two inputs, which typically R ( reset) and S (set) are referred to, if necessary, a third, typically at the C (clock ) input designated yet, to which a clock signal can be applied. With a signal at the " set" input, i.e., while, the output of the flip-flop is set to 1. If you activate the other hand, the " reset " input (ie, at the same time ) the flip-flop is reset, then: The output is then a logical 0. Then present at both inputs a 0, the flip-flop remains in the state previously set. Particular attention must be paid to the input state, in which both R and S input are active ( R = S = 1, the RS flip-flop from NOR gates or the RS flip-flop from NAND gates ). Here, the state-controlled flip-flop assumes a third state in which both outputs become the same level ( the structure of the NOR gates is 0, the construction of NAND gates 1). It is often claimed, this state is unstable, but this is not true. He gives only a logical contradiction and is therefore also called " forbidden state ". If the flip-flop clock-controlled, changes in initial conditions can of course only be made ​​if the controlling input is activated. In clock-state- triggered flip-flops a suitable edge must, accordingly, a 1 at the inputs C, with clock - edge -driven flip-flop (rising or falling, depending on the design ). An edge-triggered RS flip-flop can also enter an undefined state by ( almost ) simultaneously measures both inputs.

An input can be switched, however dominant, thus avoiding the third state. Such flip-flops are in the dominant input with a 1 after the letter. In automation technology, such as programmable logic controllers, the use of dominance is mandatory, because unstable or unpredictable conditions can not be tolerated here. The dominance is ensured by the fact that the dominant state is programmed in time after the dominated and thus these overrides, so the synchronization point ensures that the desired dominant behavior. Within multitasking systems must therefore be enclosed and must not be interrupted the execution of the set and reset. Dominant RS flip-flops were not available as individual hardware components. The dominance came only indirectly then used when a complex module equipped with reset and set inputs. A symbolic single item they only came in the sense that their function is implemented by programming.

The operation of an RS flip-flop can be roughly comparable with that of a mechanical rocker ( this comparison motivates the term flip-flop ). A rocker has two stable states: On the one hand, if its left end touches the ground, on the other hand, if the right end rests on the ground. Use appropriate effort you can convert the rocker from one stable state to the other stable state (at a flip-flop, this corresponds to the activation of the inputs, ie respectively ). Allows the controlling force (equivalent to and ) after, so the rocker remains in the state previously set: This is so as it is stored. However, a horizontal orientation of the rocker results in a metastable state ( and corresponds to the case ), since the rocker is constructed exactly symmetrically and will not all external interference can be eliminated, the rocker tilts after a certain time and occupies one of the two stable states as soon as the controlling force is released. As a rule, can not be predicted whether its left end or right end will tilt in the direction of the ground, as not all faults are precise enough known. A clocked flip-flop corresponds to a rocker, wherein the controlling force to act only for a predetermined time by an external clock signal.

In the following comparison of the first embodiment with negated signal names is carried out at the entrance. This means that the resting state of the input signals is formed by the 1- level, and the active switching state by 0 - level of the inputs. This is due to the structure of the flip-flop composed of NAND gates and quite common in practice. In the second embodiment inputs an additional inverting stage is practically laid on, so that again working with the "real" signal name.

The inputs of the flip-flops have the negated signal names R and S, as they carry out their ( active ) reset or set-function with 0.

D flip-flop

The D flip-flop (short for data or delay flip-flop for " delaying " of the signal at the data input by one clock ) appeared as a single block for the first time in the 1960s. It has a data (D) and a clock input (C of clock, often represented as a ">"). In addition to the Q output usually also exists to the inverted output. A D-type flip-flop realized the elemental characteristic function Q '= D of the clock-controlled direct transfer of the data input to the output. As long as the clock is not active, that is the current state (" delay " ) is held.

This delay is but from another point of view, a storage of the data, as long as the clock input does not trigger a new storage. In order for this type flip-flop is to be regarded as a 1 -bit memory and is often used in this function. He is then typically called " latch " (see below).

Because of their elementary operation to D flip-flops have received as a common symbol description for individual functions in highly integrated components such as microcontrollers, field programmable gate array ( FPGAs) and ASIC.

If not (referred to CE, in the German area as " delay input " V ) a so-called clock enable input is available, with which the clock input can be switched to its function ( engl. enable = enable), one speaks of a DV flip-flop.

• The clock-state- controlled D- flip-flop ( D-latch ) consists of an asynchronous RS flip-flop with an input-side " Taktzustandsbeschaltung ". This is the "forbidden" state R = S = 1 is automatically avoided. It is referred to, particularly in the English literature and to distinguish it from edge-triggered D flip-flop as a latch ( latch, bolt ). As long as the enable input E ( which is usually connected to the clock ) is active, the output of the latch follows the level that is applied to the D input. That's why we call this behavior transparent. The advantage of the D-latch is its low outlay on circuitry. The drawback is that it - like all transparent flip-flops - has a direct control of the input D to the output Q. Compared to a "count flip-flop", it can therefore be fed back not directly in synchronous circuits.

• The edge- triggered D flip-flop is directly feedback- capable as elemental transparent flip-flop. Therefore, can be realized by external wiring all other edge-triggered flip-flops and types of complex circuits such as synchronous counter, clock divider or shift register. A einflankengesteuertes D flip-flop stores the active clock edge the logic state of the input D and gives its value to Q from. Outside the active clock edge ( or possibly existing deactivated clock enable input ) there is no assumption of the input value.

JK flip-flop

A further class of flip-flops, is used in the primary discrete digital circuits, the JK flip-flop. They were likely named after Jack Kilby, but are often called Jump-/Kill-Flipflops, since the input assignment J = 1 ( where K = 0) is a 1, and for K = 1 ( J = 0), a 0 is stored. You are always edge controlled and / or as a master-slave flip-flop. The input C is for rising edges ( change from 0 to 1 ) or falling edge ( change from 1 to 0) are designed. The condition J = K = 1 is allowed. In this case, the output level changes each active edge of the clock signal, which corresponds to the behavior of a toggle flip-flop. J = K = 0, the state is maintained.

In the case of the realization of the JK flip-flop when clock-state- controlled master - slave flip-flop must be considered as a major limitation that the states of the two inputs J and K are not allowed to change during active clock state (C = 1). So then there is no pure edge-triggered flip-flop. This disadvantage is also one reason why clock-state- controlled JK master - slave flip-flops are rarely used in complex digital circuits and are primarily edge-triggered flip-flops replaced by that do not have this disadvantage.

Many of the flip-flops available in different designs combine and are so versatile.

T flip-flop

An asynchronous T flip-flop ( toggle flip-flop ) changes with each clock pulse to its initial state. His first realization in electromechanical block form became prominent in the 19th century as staircase switch and is still in widespread use in new installations. Asynchronous T flip-flop can be formed by a (synchronous ) D flip-flop, whose output Q is inverted when fed back to the D input. T stands for English toggle - switching back and forth. Especially in discrete digital circuits and the above-described JK flip-flop is used to implement a T flip-flop at times asynchronously. In this case, both inputs of the JK -FF must be set to logic "1".

An asynchronous T flip-flop is similar to a ballpoint pen or a latching relay (impulse switch ). Because of the above already mentioned property of the alternating with half the frequency of the clock signal output level of these flip-flops are mainly used as a frequency divider and as a basic element in asynchronous digital counters. They are also used in order to obtain a square wave signal having a duty ratio of exactly 1:1.

In contrast, possesses the synchronous T flip-flop (next to the clock input C) a T input. Only when this is applied to a 1, the T flip-flop synchronous with the clock switches to the other state. It may be reproduced from a JK flip-flop, for example, by J input and K input are connected to the T input. Synchronous T flip-flop is used for example in the synchronous counters.

Additional asynchronous control inputs for the flip-flop

Depending on the design the clocked flip-flops ( clock-state- controlled or edge- controlled flip-flops ) also possess additional asynchronous control inputs. The asynchronous control inputs affect the flip-flop without a clock signal. Depending on the design, these devices have an additional asynchronous reset input, an asynchronous set input or both inputs together. The asynchronous reset is sometimes referred to as "Clear" ( = delete ), while the asynchronous setting as a ' preset ' (= pre-assignment ) is called.

Through an asynchronous reset input flip-flop (output = 0), regardless of the clock be placed on the defined initial state. This function the device is used for example as an asynchronous reset when the supply voltage or if the circuit has to be brought, during operation to a defined state ( reset state ). The asynchronous set input behaves the same way as the asynchronous reset input, but brings the flip-flop in the set state (output = 1). Simultaneous operation of asynchronous set and reset input together can the flip-flop depending on the design but bring in an undefined state. Frequently the two additional asynchronous inputs are active low driven. The asynchronous reset signal can then be connected directly to a reset generator with a low- active switching output.

Timing of flip-flops

In the engineering- application of the flip-flop devices in electronic circuits various time conditions must be observed. For example, consider a taktflankengetriggerten D flip-flop with Einflankentriggerung. As a reference for each switching operation, we consider the flip-flop switching the active edge of the clock (clk ). The input signal ( D ) input of flip-flop must not be changed before the active switching edge of the clock signal for a defined minimum period. This time is called the setup time tsu (English setup- time).

Furthermore, the logic state at the D input after the active switching edge of the clock signal for a defined minimum period shall not also change. This time is called the hold time tH (English hold- time). Furthermore, there are in the flip-flops or the signal propagation delay through the device ( engl. propagation delay time ) tPD (see also runtime tolerance calculation ).

The maximum clock frequency of the clock signal fclk, max must not be exceeded. As another timing specification when clock signal occurs when you flip flop on the pulse width of the clock signal TPW, clk ( engl. pulse -width ). This minimum length of the clock signal ( start from the active clock edge and ends at the opposite clock edge of the pulse) must not be exceeded, so that the flip-flop can safely turn.

In flip-flops with additional asynchronous control inputs it must also be no change in signal for a defined minimum period before the active clock edge when the clock signal CLK at the asynchronous control inputs. Furthermore, the asynchronous control inputs after the active clock edge for a defined minimum period must not change.

If the timing constraints are not met at the flip-flop can be assumed that there is a malfunction in the flip-flops.

In the example, the timing of the D flip-flop is described. All other flip-flops with clock input, such as the T -FF, in principle, have the same behavior. With the RS flip-flop and JK flip-flop must also analogous to the D flip-flop setup time TSU and the Hold Time tH are complied with. Since these two types of flip-flop having in each case two inputs then the time setting is valid for the R- and S- input and the J and K input.

Circuit symbol of various flip-flop types

Use of flip-flops

Simple example of an elevator controller

In the simple example of an elevator control system, the memory function of an RS flip-flop will be illustrated. We consider a lift in a multi-storey building. There is a call button for the elevator on each floor. The process is known from everyday life: If you press the call button so it lights and then even when you release the button. The call command remains stored in, even if the switch does not stay pressed. The light behind the button goes out only when the elevator stopped on our floor and the doors opened. Only now also the call command is deleted. Such behavior can be realized with an RS flip-flop. For this we need a flip-flop for each floor. His two inputs ( S and R), we attach to each connected to a voltage source (HI = High), which delivers a sufficiently large voltage for a logic 1. Intermediate voltage source and the flip-flop inputs are each seated button. One button is connected to the call button each floor, the other button can only be operated from the lift itself. By pressing the call button on one floor, we short-circuit the connection between the voltage source and the S input of flip-flop, which is responsible for our floor. This is set for S = 1 and R = 0, the flip-flop: Q = 1, the output Q so that stores the call command. Let go of the button, the button snaps back, the connection between the voltage source and the input S is disconnected, the input S of the flip flop falls to 0 ( S = 0 and R = 0). However, the flip-flop remains in the state set previously: as long as Q is namely to 1, and the reset input is activated ( storage case ). The elevator is now set in motion. As soon as it stops at our floor and opens the doors, actuating a mechanism to switch connecting the R input and the voltage source. This deleted for S = 0 and R = 1, the call instruction (Q = 0) and remains cleared until another visitor pushes the call button again. In reality, the control is of course far more complex, the call commands stored in the respective floors are given to an electronic control system of the elevator, which will determine an appropriate order from these and from the pressed in the elevator car keys, after the floors are to be approached.

Widely used in digital electronics

Flip-flops may be considered as a 1- bit memory. From these registers different word lengths can be put together as they are used for example in microprocessors.

Also, the individual memory cells of static RAM comprised of flip-flop circuits. While on the other hand, there is a dynamic RAM memory cell only consisting of a capacitor and a transistor.

Furthermore, flip-flops are essential in digital counting circuits. Here especially D or T flip-flop ( of various types ) are used as a frequency divider.

In older quartz watches with hand display a chain of 14 flip-flop divides the oscillator frequency 32768 Hz through 214 and delivers pulses of a length of exactly half a second that are fed to a Lavet stepper motor which moves the hands of the clock with a mechanical gearbox.

In the applications described above, the flip-flops are typically part of a larger electronic device. In the engineering- circuit design flip-flops are used today little more than individual components. Today, typically components are used, which contain in addition to the flip-flop circuit also functions in the same device. These include, inter alia, the FPGA, PLD and ASIC devices. In these devices typically D flip-flops are included.