Layout Versus Schematic

Layout versus schematic (LVS ) is a step in the layout verification of integrated circuits. It is used to ensure consistency of the layout produced by the original circuit ( schematic ). It takes place a netlist comparison in which the used to the layout design original netlist is compared with an extracted exclusively from the circuit layout netlist.

The extraction of the netlist from the layout is done by using an extracting files. This includes basic layout structures defined, (, vertical interconnect access electrical connection between two interconnect layers ) depict such as transistors and vias, as their recognition for netlist generation is necessary. Thus, the geometric structures of the layout can be investigated to determine which functional units ( components and connection structures) they realize. This information allows the generation of a netlist exclusively from the circuit layout.