MSI protocol

In Modified, Shared, Invalid ( MSI) is a protocol for maintaining cache coherence in coupled memory multiprocessor systems.

If in such systems, each processor has a cache that needs to be set if any of the cache or the main memory contains the current value of a date. A system, which ensures at all times to obtain the current value of a date - even if it is located in another cache -, is cache coherent.

The MSI protocol is mainly used for Write- Invalidate and Write- Back cache and is based on the snooping technology.

Within the MSI protocol, each cache block is assigned to exactly one of the states Modified, Shared, or Invalid. The individual states mean:

The central starting point for guiding the change of state of each cache block is the bus. On this individual caches communicate with the main memory. Each cache has a cache controller, which at the request of a date, a corresponding command sets by the processor of the cache on the bus for example. In addition, this also monitors commands from other cache controllers or other components (such as the controller of the main memory ) to be placed on the bus. According to the own and intercepted commands the state change of the respective cache blocks are made. The principle of the monitoring operations and commands on the common bus is called snooping.

A processor can access a single address in the storage system write ( PrWr ) or read ( PrRd ). Accordingly, solving read and write operations of a processor of bus transactions. In the MSI log has the following bus transactions:

The read and write operations, as well as the bus transactions by directly and indirectly generated determine the behavior of the state machine, which is defined by the MSI log.

Extensions of the MSI protocol, the MESI protocols and MOESI.