MOESI protocol

MOESI (Modified, Owned, Exclusive, Shared, Invalid ) is a protocol for maintaining cache coherency in memory- coupled multiprocessor systems. It includes all possible states of a cache line, which are also known by other protocols ago. Each cache line is in one of five states ( cf., pp. 165ff ):

The MOESI protocol is a complicated version of the MESI protocol. It avoids writing back modified cache lines when other CPUs want to read this. Instead, the current value at each change between the caches is directly propagated (see state Owned).

MOESI offers no significant advantage over MESI, when the interconnection network between the processors and the memory controller is a bus. However, it is in direct networks of advantage, for example, AMD Opteron systems. Avoiding the write-back of modified cache lines here provides for the discharge of the interconnection network and memory controller. In addition, the communication between two or more CPUs with respect to latency and transmission rate can be significantly better than between the CPU and main memory. Multi-core CPUs with their own caches per core, this is usually the case.

In the area of ​​system on a chip can save state energy using the additional " Owned ", if this means the access is attributable to external attached storage. In the case of the AMBA Buses from ARM, the required energy of an off-chip memory access is up to ten times higher than an on-chip memory transfer between two bus masters according to the manufacturer. The AMBA bus since version 4 supports MOESI protocol.

State diagram

To improve the intelligibility and clarity of the state diagram was divided into two ( active and passive CPUs). By Machine Association can be produced, which combines both diagrams, an equivalent machine.

• State diagrams

State diagram for passive CPUs in MOESI protocol

Modified (more precisely: Modified Exclusive)

The cache has the only copy of the cache line and has modified it (dirty). When he removed the cache line, he needs to update the main memory. If a read request from another processor comes, it sends the data in this cache line to it and changes its own state owned. The state of the cache line of the other processor is set to shared. In a write notification of another processor it sets its cache line to invalid.

Owned (more precisely: Modified Shared)

The cache has a plurality of copies of the cache line. He has his cache line modified but not yet written back: In the main memory but is an obsolete (ie invalid ) value. For all other processors that have this cache line, this is in state shared. The processor is responsible for updating when writing in this cache line, all other caches. Sends another processor, a read request, the cache sends the current data directly to the requester. In a write notification of another processor it goes invalid in the state. The person who wrote, then changes its state in owned. For all other caches nothing (the state remains on shared, if the cache line exists) changes.

Exclusive

The cache has the only copy of the cache line and it has not been modified (clean, unmodified ). For a read request, it sends the data to the requestor. The states of both cache lines then go to the state Shared. In a write notification to invalidate the cache line.

Shared

The cache has a current of a plurality of copies of the cache line. A cache line in this state may only be read.

Invalid

The cache line is invalid. It is requested by the processor, a cache miss occurs and the data must be fetched from main memory (or other cache). For this purpose, it sends a request to the same memory and to all other processors. If the cache line in another cache exists and is there this modified (modified or owned ), the data from there are delivered. The messages from the memory data will be ignored, because they are not current. Was the cache line in another processor on modified, so the state changes there on owned. In each case, the state of the cache line in the cache is set to shared. The cache line is modified anywhere, the cache accepts the data from the memory. Depending on whether the other processors have the cache line in its cache or not, the new cache line in the exclusive state or shared is set. For a read request or write notification happens in the state invalid nothing.