NonStop
The NonStop technology refers particularly fault-tolerant computer systems with high availability, which are used in mission- critical, transaction- intensive applications. It was in 1974, developed by Tandem Computers and brought in 1976 with the Tandem NonStop System I for the first time on the market. After tandem was first taken over by Hewlett -Packard Compaq 1997 and 2002, the systems are now under the brand HP Integrity NonStop server part of the HP Integrity server family.
NonStop systems are generally multi-processor systems in order to continue working in the event of hardware or software failures without downtime can. With the Blade systems introduced in 2008 and multi- core processors ( dual-core and quad-core ) are available.
History and Technical Development
Foundation
Tandem Computers was founded in 1974 by James Treybig. He was an employee of HP and worked on the HP 3000 series. Early on, he recognized the need for fault-tolerant OLTP ( online transaction processing ) systems. After a switch to Kleiner Perkins Caufield & Byers, he worked for two years at his tandem idea before he called the company to life. Half of the first 18 employees were former employees of HP.
TNS stack systems
The first system was the Tandem/16 or T/16, later renamed NonStop I. In 1975, the hardware design was completed in 1976 and delivered the first system. The system consisted of 2-16 CPUs. Each CPU had its own unshared memory, a separate I / O processor, a dedicated bus; In addition, there was a redundant connection between all the CPU via an overarching backplane, called Dynabus. Each disk and network controller had to connect to two CPUs and I / O controllers. Each disk was mirrored (RAID 1 ) and had physically separate connections to two disk controllers. When a disk fails, could continue working on the mirror disk. When a CPU, a controller or bus failure, the hard drive was still accessible via alternative routes. The power supply has been designed to be redundant in the system. The system configuration was documented in so-called Mackie charts, named after the tandem employee David Mackie. No component was designed purely as a substitute, but all were also used in control mode.
The T/16 CPU had a proprietary design, closely related to the HP3000. Each CPU comprised two boards with TTL logic and SRAMs, and worked with approximately 0.7 MIPS.
The first version of T/16 had only a programming language: TAL, for Tandem Application Language. TAL was an effective, machine-dependent system programming language (for operating system, compilers, etc.), but also - could be used applications - not portable. It was derived from the HP3000 SPL language. The semantics here there were similarities to C, while the syntax on Burroughs ALGOL based. Subsequent publications supported Cobol74, Fortran, and mumps.
The tandem systems had a proprietary operating system that significantly differed from Unix or HP3000 MPE 's. The first term T / TOS ( Tandem Transactional Operating System), was soon renamed because of its ability to protect databases from hardware or software failures in the Guardian, which means " Guardian " means. In contrast to all other commercial operating systems Guardian was a message-based operating system in which all processes can communicate with each other (without the use of shared memory ), regardless of which CPU to run the processes. This approach allows cluster of principle, an unlimited number of individual computers, which was revolutionary at the time.
All important system and application processes were designed as a master / slave pairs that were running in different CPUs. The slave process was periodically dump the memory of the master process ( checkpointing ) and could take over if the master process came into problems. This allowed the application to survive error in a CPU or in a controller without loss of data. Although the checkpointing between the primary and backup process produced a certain overhead, but by far not 100% as in other systems.
In 1981, the T/16 CPUs were replaced by the NonStop II. The main difference to the T/16 was to support the 32 -bit addressing by the switchable by user " extended data segment". This enabled the next 10 years of Software development and was a great advantage over T/16 or HP3000. However, the visible registers were still a 16 -bit width, which required additional instructions compared to 32 -bit systems. All of the following systems of TNS architecture were affected by these inefficient instruction set. The NonStop II CPU had no major internal data bus, which required additional microcode for 32- bit addresses. A NonStop II had CPU board 3, with similar design as the chip and T/16, also the main memory has been replaced by the battery-backed DRAM.
In 1983, the NonStop TXP CPU was the first completely new implementation of the TNS instruction set architecture. It consisted of standard TTL chips and programmable array logic chips, 4 boards each CPU module. For the first time the cache memory was used. The CPU had a more direct implementation of the 32 -bit addressing, but still has a 16-bit data bus. An enhanced microcode allowed reduction of processor clock cycles per instruction; CPU speed increased to 2.0 MIPS. Rack, controller, backplane and bus remained the same. The Dynabus and I / O bus have already been revised in the T/16.
Up to 14 TXP and NonStop II systems were now using FOX - are interconnected (Fiber Optics Extension a fault-tolerant fiber-optic bus); a cluster of clusters with a total of 224 CPUs. This allowed further scaling to take over even the largest mainframe applications.
In 1986 Tandem introduced the third generation of CPUs, the NonStop VLX. She had 32- bit data paths, an extended microcode, 12 MHz clock frequency and was able to execute one statement per microcycle. It consisted of three boards ECL gate array chips ( with TTL pin assignment ) and an extended Dynabus at an increased speed of 20 Mb / s per link, 40 MB / s total. FOX II increased the physical removal of TNS clusters on 4 km, at that time a technical selling.
Tandem supported initially only hierarchical, but not relational databases by means of the ENSCRIBE file system. This was later extended to a relational database, called ENCOMPASS. In 1986, a tandem the first fault-tolerant SQL database and named it NonStop SQL. 1989 cross-node transactions were introduced, a feature that was unique for some time.
In 1987, NonStop CLX was introduced, a fault-tolerant system for the low price sector. The initial performance was comparable to the TXP; later versions were about 20 % slower than the VLX. The relatively small housing fit into any " copy space ". It was a CLX CPU on the board, which contained six " compiled silicon" CMOS ASIC chips. The CPU was in duplicate, and there was a Lock -stepping instead to permit maximum error detection. The pin was the main limitation of this chip technology. Micro code cache and TLB have been external to the CPU and a bus and had an SRAM memory bank. Therefore, the CLX needed at least two clock cycles for an instruction.
In 1989, the NonStop Cyclone fast, but expensive system for the top of the mainframe market was introduced. Each CPU had 3 boards with ECL gate array chips and memory boards. Although she was micro- programmed, the CPU was designed superscalar and managed two instructions per cache cycle. This has been accomplished by separate microcode routines for each pair of common instructions. This common pair of instructions handled the same work as individual instructions in normal 32- bit systems. Cyclone processors were installed in four packages that were connected with a fiberglass version of the Dynabus.
The German Federal Railroad used such a system as a central server for the System Course 90th
Was founded in 1974 as a tandem, each computer manufacturer had its CPUs ( with a proprietary instruction set and own compilers, etc.) design and build themselves. According to Moore's Law is still valid today fit through the progressive development of semiconductors from year to year more circuits in a chip, thereby placing them in continuously exponentially growing order of magnitude faster (and therefore cheaper). Because of the rapid product cycles and the high pace of innovation, it became increasingly expensive for the computer industry to design their own chips and build. Approximately from 1991 could only be the largest computer manufacturers to make their own competitive chips. Tandem was not large enough for this process and, therefore, had to change its NonStop product line on chips that were produced by others.
Tandem formed a partnership with MIPS and used the R3000 and the following chipsets. NonStop Guardian systems that used the MIPS instruction set, were called TNS / R machines.
In 1991, Tandem Cyclone / R, also known as CLX / R before. This low-cost system based on CLX components, but used R3000 microprocessors instead of the slower CLX- processor boards. In order to bring the system to market quickly, was delivered at the beginning no native MIPS software. All programs, including the operating system, NSK and the SQL database has been compiled to TNS stack machine code. The resulting object code is then translated during kernel installation phase for the MIPS instruction set. The tool used for this purpose was the Accelerator. But the application programs could be carried out by means of a TNS code interpreter without translation in the MIPS instruction set. This migration technique was very successful and is still used today. To exclude Processor failure, two processors running in lock - stepping.
In 1994, the NonStop Kernel with a Unix-like POSIX environment called Open System Services ( OSS) has been extended.
In 1997 Tandem introduced the NonStop Himalaya S a series; their new system architecture based on ServerNet connections. The many rapid ServerNet replaced thus the Dynabus, FOX and the I / O bus. Tandem ServerNet designed for your own use, but published the concept at the same time, so that it eventually developed into the InfiniBand industry standard.
All S - series systems used MIPS processors, the R4400, R10000, R12000, R14000 and.
Due to the declining business of the former Silicon Graphics MIPS producers and the success of Intel's Pentium Pro no new investment in the MIPS processor series were more made , so that tandem in turn had to look for a new competitive processor.
Acquisition by Compaq, attempted migration to Alpha
Jimmy Treybig remained until 1996 CEO and dynamic center of the company which he had founded.
Compaq x86 -based server line was one of the first users of the ServerNet / Infiniband technology. In 1997, Compaq took over the company Tandem Computers to balance their own company's focus on personal computers. Compaq took over as Digital Equipment Corporation and its DEC Alpha RISC server. After interim considerations to use their Alpha processors, the decision was ultimately for it to migrate to Intel Itanium 2.
Acquisition by Hewlett Packard, TNS / E migration to Itanium
2002 Compaq merged with HP. In a way, tandem crossed the path of a style inspired by HP Startup with subsequent phase as a competitor of HP back to its roots as a separate line of servers from HP.
The system design supports lock- stepping in the form of dual (DMR ) and triple mode redundancy ( TMR), with either two or three physical processors per logical processor Itanium. The TMR version will be delivered to customers with the highest availability requirements. This architecture is named NSAA, NonStop Advanced Architecture.
In 2008, HP introduced the NonStop Multicore Architecture ( NSMA ). By the use of standard hardware, the cost could be further reduced. The HP NonStop Blade systems use multi-core processors ( dual-core and quad-core ).
Java, open source and Eclipse
HP ported increasingly open source software on the NonStop platform and offers it as a product, such as SOAP, Java Server Pages (Tomcat pathway ) or JBoss ( from 2013 ). In addition, several open source Java frameworks ( MyFaces, Axis2/Java, Spring, Hibernate = SASH. ) Have been certified in order to implement on the platform along with the HP NonStop Development Environment for Eclipse Java projects.
In November 2013, HP has announced plans to expand the NonStop technology to the x86 server architecture.