P6 (microarchitecture)

P6 was the Intel internal name for the first 86 processors of the sixth generation. With the development of so-called P6 architecture was begun in 1991.

The first processor of the P6 family was the Pentium Pro of 1995, based on the most successor models such as Pentium II, Pentium III, Celeron, but the Pentium M and Core. Rarely should the core of a CPU so expect a long life, such as the P6. Also in the meantime developed as a replacement NetBurst architecture of the Pentium 4 was abandoned in favor of P6.

Main architect was Robert Colwell.


The architecture of the P6 is designed with their relatively short pipeline to more moderate clock rates and achieve their performance, mainly due to a high number of instructions per clock cycle ( instructions per cycle (IPC ) ). Nevertheless, the clock rate of 150 MHz while initially P6 of the Pentium Pro was increased to 1400 MHz with the Pentium III -S.

At P6, some techniques were for the first time at 86 processors are used:

  • Superscalar pipelined architecture super
  • Fully into the CPU design of integrated L2 cache, partly on- the, partly as external chips.
  • Wide 36 -bit address latch that allows more than 4 GB of physical memory.
  • Speculative execution, and out-of -order execution for increasing the speed of execution
  • Register renaming for a more efficient processing of instructions in the pipeline.

Members of the P6 family

  • Pentium Pro
  • Pentium II
  • Pentium III
  • In some ways, the Pentium M and the Intel Core microarchitecture
  • Some Celeron
  • Some Xeon