Register-transfer level

The register transfer level, Eng. Register Transfer Level (RTL ) is an abstraction layer in the hardware modeling digital circuits. In the design at this level, the system is specified by the signal flow between registers.

RTL is used in hardware description languages ​​such as VHDL and Verilog, to generate high-level representations of circuits. Of these representations can be at lower levels and finally synthesize the actual hardware.

With software tools can the RTL description translated into a netlist, from which eventually a physical layout is generated by placement and routing.

The synthesis, which generates a logic circuit of a RTL model, called RTL synthesis.