A serializer / deserializer ( SerDes abbreviated ) is of data broadcasting in digital technology, a combination of special multiplexers and demultiplexers that are shared between two parallel series endpoints. To be transmitted parallel data is converted into a serial data stream serializer high bit rate, transmitted serially, in parallel, and output again to the de-serializer for further processing. The serial interface, standard communication media are symmetrical signal transmissions using Low Voltage Differential Signaling (LVDS) or fiber optic (FO), with respect to the parallel port transparent. The advantage of the SerDes is to lower the number of lines in comparison with parallel transmission, and the avoidance of clock skew, which is particularly advantageous in backplanes.


Called The serializer, in this context as English Parallel In Serial Out ( PISO ), typically and in the basic equipment of a parallel data input word lengths of 8 to 24 bits are common to the serial output and a clock line is not shown in the figure, which indicates the arrival of a new data word. The deserializer also known as English Serial In Parallel Out ( SIPO) is to set up almost a mirror image and consists of a serial input and parallel output data.

The primary basic function is realized by shift registers, in addition SerDes possess additional functional units for clock generation on the side of the serializer and functional units for clock recovery on the part of the deserializer. These various forms of phase-locked loops (PLL ) are used.

There are four basic SerDes method which are described in more detail below. The complexity of the single process increases downwardly.

Parallel clock SerDes

The serialized data stream is sent to a separate reference clock. The advantage is the slightly lower amount of circuitry. The disadvantage is that two lines for the transmission ( serial data and clock line ) are necessary and thus the problems of clock skew ( clock skew ) can be reduced only by additional measures. First available SerDes procedures were constructed on this principle.

Embedded Clock SerDes

In the serial data transfer clock signal is additionally integrated (English embedded) and the deserializer uses it to receive clock in the serializer. The advantage is that only a transmission line is necessary, and problems are reduced by the clock signal deviation. A disadvantage is the significantly higher amount of circuitry for synchronization and clock recovery.

8b/10b SerDes

In this SerDes method additionally a line code is used by the eponymous 8b10b code. The advantage is that the resulting serial signal is DC component and therefore can be transmitted via pulse transformers or optical waveguides.

Bit-interleaved SerDes

In the bit-interleaved SerDes, German as " bit - interleaving ", more serial streams to be construed as parallel data signal and combined with appropriate line coding to a higher-level, high-frequency data stream by interleaving. This process is sometimes counted among the field of SerDes method, although it has functional overlap with typical multiplex methods from the field of telecommunication networks for wide -area data communication such as the Synchronous Digital Hierarchy (SDH ) and SONET.


  • Interface (Software)
  • Peripheral bus (internal)
  • Digital technology