Shallow trench isolation

The grave insulation (english shallow trench isolation, STI, also box isolation technique, BIT ) is a method of semiconductor technology for electrical isolation of individual components ( usually MIS field effect transistors ) on integrated circuits (IC). To about 250 to 700 nm deep trenches are created and filled with an electrically insulating material (typically silicon dioxide) is filled between the electrically active areas. A similar process is applied to other semiconductor products, for example in Hochleistungsbipolartransistoren or analog integrated circuits. This grave depths of about 5 microns are used. To distinguish them from the " shallow grave isolation" (STI, shallow dt = flat), this process is called " deep grave isolation" ( engl. deep trench isolation, DTI, deep = dt deep) respectively.

In addition, there are a number of different isolation methods that also use a more or less deep trench is filled with electrically insulating material.

Background

The STI technique has long been the preferred isolation technique ( for electrical insulation individual components ) in CMOS circuits (especially for technology nodes below 0.25 microns ). The procedure was developed as previously used techniques (especially LOCOS process and extensions ) are no longer sufficient to (English feature size ) to ensure at the used minimum feature size sufficient insulation. The LOCOS technique was doing some major drawbacks, for example, limits the formation of " bird beaks " the packing density and the insulation effect is rather superficial. Furthermore, the LOCOS technique influences the topography of the chip surface is negative, so that subsequent steps can be carried out due to the poor lithographic patterning is impeded. The main disadvantage of the STI process over LOCOS is the higher number of process steps.

STI process

The STI process is usually one of the first manufacturing stages in the production of integrated circuits. Starting material is an unstructured silicon wafer. The layer thicknesses indicated in the following basic description are approximate only and may vary significantly in processes actually used to some extent.

The first process section (Fig. 1), the deposition of the layer stack, which is structured later. For this purpose, a very thin silicon dioxide layer by thermal oxidation of silicon initially produced (about 20-40 nm). This oxide for the subsequent silicon nitride layer as a buffer layer to reduce lattice constant and different size of the thermal expansion coefficient resulting mechanical stresses, thus improving the adhesion of the nitride layer. The oxide is then via chemical vapor deposition at low pressure (English low pressure CVD, LPCVD) silicon nitride layer having a (approx. 100-150 nm), coated; the nitride layer is used later as a stop layer for the CMP process ( engl. chemical- mechanical planarization ). Finally, the application of a photoresist is performed by spin coating.

The subsequent second process section (Fig. 2) is the exposure of the subsequent isolation wells. For this purpose the previously applied photoresist is photolithographically patterned and thus masks the later grave areas. After that, anisotropic etching of the layer stack and the grave areas done (approx. 250-700 nm deep), for example, by reactive Ionentiefenätzen ( DRIE ). To remove polymer residues of RIE step, followed by a brief wet chemical etching with hydrofluoric acid solution ( hydrofluoric acid ), which also slightly undercut the buffer oxide ( Fig. 3).

Then filling the trenches with the insulating material is carried out of silicon dioxide. The deposition takes place over the entire surface by a CVD method to overfill the trenches. The CVD process has to have the ability to fill smaller structures with higher aspect ratios homogeneous. This is possible, for example, with HDP - TEOS - PECVD ( high-density plasma tetraethylorthosilicate plasma enhanced CVD). To obtain a higher quality interface between the silicon and the CVD silicon dioxide, which is an interface with few interface charge, a thermal silicon dioxide is often faced with the CVD coating again generated in the grave space, called the liner oxide (Fig. 4, about 20-50 nm). Among other things, also caused by the etching process damage and mechanical stress to the grave edges are reduced.

After filling of the trenches, the wafer is entirely covered with nitride, and a layer system comprising silica. The subsequent manufacturing steps, such as the structure of the transistor structures, it is therefore necessary to expose the silicon substrate again. This is done in order to improve the surface of the wafer ( topography ) - particularly important for photolithography - by the removal of overlying layers of the wafer by chemical-mechanical polishing (CMP) of silicon dioxide, the so-called oxide CMP. The silicon nitride is used as a stop layer for the polishing process. Then also follows the wet-chemical removal of the silicon nitride stop layer ( with phosphoric acid ) and an etch-back of the remaining oxide with hydrofluoric acid, to the buffer oxide is removed.