SSSE3

SSSE3 ( Supplemental Streaming SIMD Extensions 3 ) refers to the changes introduced by Intel's Core architecture extensions of the SSE3 instruction set. Corporate are also the terms " Tejas New Instructions " (TNI ) or "Merom New Instructions " (MNI ) was used. SSSE3 is often mistakenly referred to as SSE4, but is a completely different SSE4 instruction set dar.

New Commands

SSSE3 extends the SSE3 instruction set with 16 new commands. Since these can be applied to both 64 -bit MMX registers as well as 128 -bit SSE registers, Intel indicates that there were 32 commands.

  • Psignw, psignd, psignb
  • Pshufb
  • Pmulhrsw, pmaddubsw
  • Phsubw, phsubsw, phsubd
  • Phaddw, phaddsw, phaddd
  • Palignr
  • Pabsw, pabsd, pabsb

SSSE3 was presented as part of the Intel Core microarchitecture, and the first time in the processor cores Merom ( laptop ), Allendale / Conroe (desktop) and Woodcrest (server) integrated.

  • Intel Atom (all processors)
  • Intel Celeron (from processor core Conroe -L)
  • Intel Celeron M (from the processor core Merom -1024 )
  • All processors of the Intel Core 2 series
  • All processors of Intel 's Core i - series
  • Intel Pentium Dual-Core
  • Intel Xeon ( Woodcrest core from processor )
  • VIA Nano
  • AMD Bulldozer
  • AMD Fusion

Footnotes

  • Processor architecture
  • Intel
Intel Core (microarchitecture) Desktop-Computer Host (network) Bulldozer (microarchitecture) Advanced Vector Extensions Multiply–accumulate operation#Fused multiply.E2.80.93add
743477
de