Static random-access memory
Static random-access memory ( German: static RAM Abbreviation: SRAM) means an electronic memory chip. Its content is volatile ( volatile, volatile engl. ), That is, the stored information is lost when the power supply is removed. In contrast to dynamic memory ( DRAM), which for the avoidance of data loss periodic refreshing ( engl. refresh) needed, the data content can be stored at the operating voltage of any length in the static RAM, which is derived the name of this type of memory.
Features and Construction
The information is stored by a change of state of the bistable multivibrator in the form of a flip-flop per bit. Although it allows to read out the memory cell very quickly, but when compared to the dynamic memory cells, the memory cell is relatively large. In the static mode ( holding the information) of the power requirement of a cell is very small.
SRAMs are now mostly as a 6- transistor cell ( 6T - SRAM ) cell manufactured using CMOS technology. The structure of a flip-flop circuit with resistors as load elements (so-called 4T SRAM cell ) is no longer used; instead of the load resistors of p- channel MOS transistors are used today. With another two transistors for coupling to the column and row - select lines to the said six - transistor cell results attached in the picture. Because of this complex structure of an SRAM cell in comparison with a DRAM cell consumes significantly more die area ( about 140 F ²). In principle, therefore, each bit is stored in the SRAM cell in four transistors which form two mutually -connected inverters. This memory cell has two stable states, which represent 0 and 1. The two additional access transistors are used to control access to the memory cell during read and write access.
In addition to the 4T and 6T SRAM design, there are numerous alternative variants using additional transistors additional functions (eg separate read port ) or special characteristics (eg, lower leakage current, lower power consumption when writing, greater stability ) are to be realized. The names used for this purpose 5T, 7T, 8T, 9T, 10T or 12T SRAM cell but are not limited to a specific design, see
Operation
An SRAM cell has two different states. These are: Standby ( waiting for access ), read access ( memory state has been requested ) and write ( memory state is overwritten). These states work as follows:
Standby
When the word line is not connected, the access transistors separate the memory cell of the bit lines. The two gegenverschalteten inverter ( transistors M1 -M4 ) strengthen its current state each each other ( as long as the operating voltage is applied ).
Read access
Let us assume that the memory state is set at Q to a logic 1. The read access starts with this charging of the two bit lines to half the operating voltage, followed by switching the wordline to switch through to both access transistors. As a second step, the respective values of Q and Q are transferred to the bit lines, ie BL and BL will be charged via M1 and M5 is discharged to logic 0 (M1 is turned on, because Q is set to a logical 1). BL is charged by M4 and M6 via the supply voltage to the logic 1. If the memory state previously would have been 0, the behavior would be correspondingly opposite. The difference between BL and BL can then be read by a sense amplifier.
Write access
The write access starts with the value to be written is placed on the bitlines. So if we want a 0 write BL is set to 0 and BL to 1. When writing a 1, the two values are mixed up. Subsequently, the word line is then turned on so that the value is written into the memory cell. This works because of the relatively weak transistors which constitute the inverter, can be overridden by the relatively strong bitlines. An appropriate sizing of the transistors is necessary in the production, thus overwriting works flawlessly.
Interfaces
SRAMs are available with different interfaces. As a discrete component, primarily for direct connection to microcontrollers, asynchronous bus interfaces are parallel to the application. Feature is that, the access to the memory without clock signal. The access time per memory cell is determined by the runtime and is in the range from 5 ns to about 100 ns. Moreover, there are synchronous SRAMs, in which the access is carried out synchronously with a clock signal. Generally the rate of the synchronous SRAM is higher than with asynchronous SRAM, since the synchronous interface is the possibility of the addresses defined by means of a pipeline to the data transfer time. This brings speed advantages especially with sequential memory accesses. An example of synchronous SRAMs are the so-called " ZBT SRAMs " (English zero- bus- turnaround SRAM), which are found in fast graphics memory application. For use in combination with DDR and " Quad" memory, there are also SRAMs transferred on both edges of the clock signal in accordance with more data; Here are sizes up to 72 Mibit ( in the organization 4 Mi × 18 or 2 × 36 Mi ) achieved at a clock frequency of 400 MHz.
Applications
SRAMs are used as high-speed memory with relatively small data capacity used in applications where the data content must be quick to access, such as in a cache processors and digital or mixed-signal ICs such as FPGAs as a local on-chip memory.
Furthermore, SRAM is used in devices where the data content without permanent power supply to be backed up to a few years. Since the power consumption in the static state is ( no memory accesses ) of a few nA, a small backup battery is sufficient (possibly a capacitor ) to provide the required supply voltage, for example when the CMOS RAM to store BIOS settings in commercial PCs. This application places the SRAM in combination with a mostly exported in the form of a lithium battery backup battery a special form of NVRAM (English non-volatile random-access memory, non-volatile RAM) represents the battery can be integrated in the chip housing of the memory module.