Translation Lookaside Buffer

The term translation buffer or English Translation Lookaside Buffer (TLB, see also cache ) denotes a functional unit of memory management by itself nachladenden memory management units (MMU ).

If virtual memory is used, the virtual must be converted into physical addresses. The virtual or logical address is translated at x86 in three steps using the segment and the most organized tree-like page table to physical address, other processors (ARM, PowerPC, MIPS, etc.) operate similarly. This time-consuming computation is buffered for reasons of data processing performance in the TLB. The TLB can hold a limited amount of these references ( usually not more than 1024 entries ) and can accelerate the execution of memory accesses considerably. This is realized via associative order registers that allow parallel access. Thanks to its design, the TLB is very expensive per entry.