MIPS architecture

The MIPS architecture (English Microprocessor without interlocked pipeline stages; German about, microprocessor without pipeline lock ' ) is an instruction set architecture RISC - style, which was developed from 1981 by John L. Hennessy and his colleagues at Stanford University. The development took place starting in 1984 at the newly-founded MIPS Computer Systems Inc., now MIPS Technologies.

MIPS was originally a 32 -bit architecture, the 64- bit expansion took place in 1991 and was introduced with the R4000. Many RISC architectures from this period influenced each other, these include Sun SPARC, DEC Alpha processor or Hewlett- Packard's PA -RISC.

The MIPS architecture uses the register / register-execute model.


MIPS processors were Silicon Graphics Unix workstations (eg SGI Indigo2 ) and Unix servers used (eg SGI Origin2000 ). Previously offered other workstation manufacturers such as Digital Equipment Corporation ( DEC) machines with MIPS processors, such as the DECstation family (2100, 3100, 5000 ) and the DECsystem under the Ultrix operating system. For example, Siemens equipped or SNI their server the RM series with MIPS processors R4000, R5000 and R10000 family.

MIPS processors are also often used in embedded systems. These include, for example, Cisco routers, Sun Cobalt servers to RaQ/Qube2, BMW navigation systems, the Fritz! Box, satellite receiver, Dreambox, Konica Minolta DSLRs and Sony and Nintendo game consoles.

There were attempts to speed, MIPS processors using the ECL technique. It used to the type Mips R6000, ultimately an ECL version of the MIPS R3000. This processor type was the company Control Data Corporation used in computers of the type CDC 4680.


A command in these processors is processed in several stages in a pipeline so that multiple commands ( get about command decode command and fetch operands, execute command with operands, read memory or write and the result write back ) in different processing steps simultaneously in the processor to be can. If a subsequent command to the result of a preceding relies, the following command must be stopped eventually, until the result is available. This is normally achieved by locks ( Locks / Stalls ). Another possibility for the processing of such data hurdles is the so-called " Forwarding", in which the need for the following command calculation results are sent directly after calculation to the next instruction rather than retrieving the value in the next possible cycle from a register.

The MIPS architecture waived such locks and requires the assembly language programmer or compiler appropriate measures such as reordering or inserting null operations ( NOP). This architecture can be kept simple.

Another mechanism, which serves to accelerate the MIPS architecture is the so-called Superpipelining. In contrast to spatially parallel architectures (e.g., the VLIW processors) a temporal parallelism of the command processing is achieved by division of the instruction pipeline stages in more herein. The result is a finer subdivision of the assembly line. The stages of the pipeline have in this way a shorter cycle time, and therefore, the clock rate can be increased. Superpipelining was first implemented in the MIPS R4000 processors.

MIPS processors


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