The VME (Versa Module Euro Card -bus ), and VME bus or VME bus system called, is a multi-user bus system for the control technology that was originally developed in 1981 for the Motorola 68000 processor family. Currently, the VMEbus supports almost all processors, such as Intel x86, the HP PA -RISC, Motorola 88000 and PowerPC. It has been standardized by the IEC as ANSI / IEEE 1014-1987.
The original version had a 16- bit data bus and 24-bit address bus, were developed for the various later extensions. With the current version VME64 are 64 slots available. The VMEbus is used among others in the aerospace industry, the computer of the ISS based eg on the VMEbus, albeit in a different form factor.
The bus is a backplane bus (backplane without its own electronic components) for 19 " rack mount chassis.
It was designed by a consortium VMEbus to the company Motorola and Philips. Companies that develop and market the VMEbus components are in the VITA ( VMEbus International Trade Association), users have also joined forces in organizations.
In competition with the VMEbus, the company Intel has brought a similar bus based on the 80x86 processors under the name Multibus II on the market, but by far not as successful as the VMEbus and its further developments.
- 2.1 interrupts
- 2.2 Bus Control
The boards and modules (slots ) are fitted with connectors according to DIN 41612 and IEC 603-2 on the VMEbus. These have 3 rows, each with 32 contacts, ie 96 contacts per connector. Depending on the configuration, the terminals P1, P2 and P3 ( newest addition - only in the VXI bus ) occupied.
General information about the connections
On the P1 port bus and interrupt, the data bus D00 to D15 and address bus A01 to A23 are housed.
P2 contains the connection in the middle row (row B), the data bus D16 to D31 and the address bus lines A24 to A31. Rows A and C are not defined in the VMEbus, these are unoccupied, defined by the user occupied or used by a sub-bus. As a sub-buses VMX or VSB are defined.
The P3 port contains the extensions to the VXI bus.
Pin assignment to P1
The Bussteuerungsleitungen are used to access and share the data bus. This includes the lines / BR0 to / BR3, they are the bus requests ( bus request ), they are active low. Each slot can start a bus request, in which the corresponding line is set low.
The lines / BG0OUT to / BG3OUT are the Busfreigaben (Bus Grant) as outputs / BG0IN to / BG3IN analogous to the inputs. These lines are connected such that an output / BGxOUT each is forwarded to the next slot in the input / BGxIN. This daisy-chain wiring allows you to share the release of the next slot. Unused slots must be bridged with jumpers, since the propagation chain is otherwise interrupted. This technique ensures that the four bus requests can be used by any number of slots, but this leads to the side-effect that slots left have continued a higher allocation probability.
If a slot has the bus, then he shows it by an L on the line / BBSY (Bus Busy). The counterpart to this is the line / BCLR, which is driven by the arbiter and with an L asks the slot, the bus release again to stop the transfer.
With the line / DTACK (Data Acknowledge) is indicated by L, that a data bus transfer was successful. With an L on the line / BERR failure of the transmission is indicated.
The lines DS0 and DS1 put together with LWORD tight ( within limits) AD01 which data groups of 8 -, 16 - or 32 -bit word are on which data lines. This somewhat confusing method made it possible to transfer data sets to different bus widths and different address spaces.
In addition, the lines AM0 serve to AM6 assigning address spaces and modes of transmission. It is between 16 -, 24 - and 32-bit address spaces, either block and byte / word transfer between data and program transfer, with or without privilege.
The interrupt requests via the lines IRQ1 to IRQ7. Unlike the Arbitierung the interrupt may be handled by other than the first slot. For this purpose, a line IACK (interrupt acknowledge) is carried out as an output, which is in front of the first slot to IACKIN, which is then passed as the bus arbitration always IACKIN and IACKOUT. In the drawing, red are the connections that are bridged by a jumper in the absence of insertion. There are only 3 of the 20 possible slots located, the series would continue as always. There is only one such channel IACK, the number of the interrupt that is being treated is transferred to the address bits A1 through A3.
Interrupt and bus control make an arbiter is required that controls the interrupt and bus requests. In general, the arbiter in the first slot is arranged.
The VMEbus has seven IRQ lines that have different priorities. Each interrupt can also be used by any number of blanks since the interrupt vector is not determined by the IRQ line, the requesting board outputs the interrupt itself. Specifically, an interrupt request is made so that in the first step, the requesting unit the interrupt request ( one of IRQ1 to IRQ7 ) relies on L. The unit, which is responsible for the handling of interrupts, fetches the highest priority access to the bus, if he does not have these anyway. The unit then sends to A01 to A03, the number of interrupt requests to be processed and an L on the line / IACK. The signal is then passed over / IACKIN and / IACKOUT from left to right of a slide to the next, the first unit, which has made this request, sends on the data bus D00 to D07 back to the actual interrupt vector ( 00h to FFh). This interrupt vector is then processed.
The great advantage of this method, which seems once unnecessarily complicated, is that many units can share the IRQ lines, without thereby provoking interrupt conflicts, as in the ISA, VLB and PCI bus always happens. It should be noted that the VMEbus has been historically developed before the bus systems just mentioned and introduced in the market.
The VMEbus is a multi- master bus, which means that multiple bus master can occupy the bus. Here again worked with priorities, there are four BRQ lines are available that are strictly priority assigned or work in the round robin method with rotating priorities. With the latter a fairness process is operated for longer waiting units are preferred. But Common is the pure priority methods.
The arbiter for bus arbitration located generally at the first insertion position, because there is no common BGx line. An arbiter, sits in a different place can control only the units that are mounted to the right of it. Thus, the slots would be left lost it.
VMSbus and VMXbus
The VMXBus ( Extended VME bus) specifies the connection of a memory. The data path is 32 bits wide to this, an address consists of 24 bits, which is transmitted in the multiplex as two 12 -bit words. A ribbon cable realizes the connection between the two cards.
About the VMSbus (VME Serial bus) messages with 200 to 400 MB / s are transmitted.
- Opto lynx