Arithmetic logic unit
An arithmetic logic unit (English arithmetic logic unit, therefore, often abbreviated ALU ) is an electronic calculator, which comes in processors used.
Functions
The ALU calculates arithmetic and logical functions. Logically, it can perform at least the following minimum operations:
- Arithmetic: Addition ( ADD)
- Negation (NOT)
- Conjunction ( AND operation, AND)
Typically, however, are also the following additional operations that also means the top three at the expense of computation time can also be modeled (in several cycles ):
- Arithmetic: Subtraction ( SUB)
- Multiplications (MUL ) by means of multiplier
- Comparison ( compare, CMP)
- Disjunction ( OR operator, OR)
- Contra- ( Exclusive - OR operation, XOR, EOR)
- Right and left shift ( right, left Shift, ASR - Arithmetic shift right, ASL - Arithmetic shift left LSR - Logical shift right, LSL - logical shift to the left)
- Left and right rotation (ROL, ROR)
- ( Set, clear, and test bits) register manipulations and bit changes
- Decimal Adjust after Addition
Most ALUs handle fixed point numbers. Only some special ALUs, primarily on digital signal processors, GPUs and modern PC processors that can process floating point numbers, or both formats directly.
Design and operation
An ALU can usually link together two binary values with the same number of digits ( n ). We speak of n-bit ALUs. Typical values for n are 8, 16, 32 and 64 are, for example, analog, the terms 32- bit or 64 -bit CPU is used when talking about the processor, in which these ALUs may be used.
The n-bit ALU is generally composed of single bit ALU - 1 to pass on each of the most significant ALU, a carry bit, having a carry at the respective position is identified. To switch the series 1-bit ALUs in the required function type, each 1-bit ALU, in addition to the inputs for the to be linked values and the carry bit still an input for a control vector ( Op. Code ), the from the control register ( operation register, OR) is read.
The status register
The total n- bit ALU, excluding the output vector for the result still an output vector to signal their condition. This output vector is in the status register (also condition code register ) is stored.
This register usually contains four status bits. The individual values of the status register can be polled by machine language instructions, and thus influencing the further course of the program (eg, conditional jumps ):
- Carry bit (C for engl carry bit. ): Displays the transfer which is ( the highest point ) of the operands is formed upon addition of the n -th bit. It is used as an indicator for over range when viewing the result as an unsigned number (positive results ). If the calculation is in 2's complement representation ( negative numbers possible) so the carry bit for the overrange plays no direct role.
- Overflow bit (V for engl overflow bit. ): Displays the number of range in 2's complement invoice to (carry the second highest point of the operands ). Other possible terms are in addition to V or even OF O.
- Zero bit (Z for zero bit engl. ): Indicates whether the result of the previous arithmetic operation is zero ( becomes 1 when contents of the accumulator register is 0).
- Negativbit (N): Set when the operation result can be interpreted as a negative number ( most significant bit of the accumulator = 1).
Depending on the ALU type, there are other flags, for example:
- Half Carry bit (H): Indicates a transfer between the low and high nibble. Interesting for the decimal correction when converting binary representation in binary.
- Parity bit ( P): Displays depending on the processor an even or odd parity of the accumulator (the number of bits with the value 1 is even or odd ).
Related systems
Parallel Logic Units ( PLUs ) are specifically tailored to bit manipulation ALUs. You can parallel, so get it at the same time to other computing devices to the data and are therefore subject to its own data path to the memory. PLU is a component of some types of signal processing to be used as a high -speed controller.