An XOR gate (of English. EXclusive OR, exclusive OR, " either or ") is a gate with multiple inputs and an output, wherein the output if and only logical " 1" if at an odd number of inputs " 1 "is present, and on the remaining " 0 ". The XOR operation is referred to as an anti - or contra-.
For the simple case of an XOR gate having two inputs which means that the inputs must be wired differently to get a "1" at the output. Lie either on one or the other input must be " 1". In contrast to a simple ORing the condition will not be met if a " 1" is present at both inputs. XOR with the result in this case is a "0".
- 4.1 Addition of binary numbers
- 4.2 cryptography
- 4.3 checksum
- 4.4 Frequency doubling
- 4.5 Switchable inverter
In the literature, the exclusive-or is marked with different symbols. The usual practice is to write out the operator as " XOR ", for example, the expression " A XOR B". When using the " " symbols for the logical or the symbol "" is used for the exclusive-or. When using "∨ " for the logical Or on the other hand " ⊻ " is used for the exclusive-or. As Bitwise operator is in C ( and programming languages derived from it ) the character ^ use.
The equal sign = shows the currently valid in Germany circuit symbol that only in a one of the inputs (high, logic 1), the output is 1.
The left figure shows the structure of an XOR gate from four NAND blocks according to the logical exclusive OR
The right figure shows the structure of an XOR gate of NOT, AND, and OR blocks. Due to the large number of different components, however, are not relevant for implementation in hardware is:
The function of an XOR gate with more than two inputs is obtained by first two of the inputs are XORed, then the result with the next input XORed as long are taken into account to all inputs.
The order of the inputs does not matter. The XOR operation satisfies the associative law.
The XOR operation can be calculated by the addition of two bits modulo 2. To be calculated is the simple sum of the input signals, the sum divided by 2 and then looks at the remainder of the division. Is the sum of an even number, the remainder is zero, it is odd, then the remainder is equal to one. Furthermore, one can view the simple XOR operation of two input signals as a display of the inequality of the input bits. This also applies to any even number of input signals.
Addition of binary numbers
An XOR gate may be used for addition of binary numbers. Here, in addition, for example using an AND gate, the condition X = 1 and y = 1, a so-called carry-over = 1 is formed. This carry is considered in the addition of the next higher bit to be "1 ". The adder of the Von Neumann adder logic uses this.
The proven secure encryption method One -time pad is usually implemented with the aid of an XOR operation. The message to be encrypted ( plaintext ) is to first encoded as a bit string. A second random bit sequence that is as long as the message is used as the key. The ciphertext generated by the first bit of the message with the first bit of the key is XORed, the second bit of the second and so on. If we introduce then the same XOR operation with the ciphertext and the key out, you get back the original message.
0101 XOR 1011 = 1110 1011 XOR 1110 = 0101 0101 XOR 1110 = 1011 For two bit strings, adopted 0101 and 1011, the parity is formed by means of the XOR operation: 1110 ( first line in the example on the right ). This parity has to be transmitted or stored along with the two bit strings. Is now the first bit string (0101 ) is lost, it may be restored by the second bit string ( 1011) is XORed with the parity (second line). Similarly, the second bit sequence could be recovered (third line).
A very simple frequency doubling of square waves in the frequency range up to several 100 MHz can be achieved with an XOR gate, if one feeds an input directly and the other with a slightly delayed signal ( RC element). The resulting spikes are phase- bound and about as short as the time constant of the RC element. Since this method does not use a resonance filter, the input signal can have any desired duty cycles and to be strongly frequency modulated.
At an input there is a signal, the other serves as a control input. If the control input to logic " 0", the signal is passed without modification. The control input to a logic " 1", the gate acts as an inverter.
The implementation shown earlier from And and Or gates requires 16 transistors in CMOS technology. A direct implementation (right) requires only 12 transistors and tricks below sacrificing speed, even only 6 transistors. To clarify: T1 T2 and T3 T4 invert the input signals. With the high potential at both inputs (A B ) are derived T7 T8 and pull the output Y at low potential. If both inputs are at low potential lead T11 T12, since there is both an inverter and the input signal reverses.