Charge trap flash

Charge- trapping memory, English charge- trap flash CTF is a semiconductor memory technique that is primarily used in the EEPROM, and in high-capacity, non-volatile flash memories, which are arranged as a NAND flash or NOR flash. In contrast to the alternative floating gate flash memories, the charges ( engl. charge) not stored on an electrically insulated gate polysilicon between the channel and the control gate at CT - saving, but the electrons and holes are at adhesion sites (engl. trapping center) of a layer of silicon nitride, which is separated from the channel by a thin tunnel oxide layer is held.

The advantage of using charge-trapping flash memory with respect to floating gate flash memory is in a higher density per unit chip area, which means a higher yield, less process steps in the manufacture of the memory chip, the easier possibility to integrate the flash memory with the other semiconductor circuits such as a microcontroller in a chip, and an increased number of write cycles. Charge- trapping memory were used until the early 2000s, especially in smaller EEPROM memories, while designed for high storage capacity NAND flash were first implemented primarily with lower-cost floating-gate transistors. Due to the advantages of charge-trapping flash memory NAND flash are also increasingly performed his upper memory segment by means of charge- trapping memory since the mid- 2000s.

History

The first charge- trapping memory go to work by H. A. R. Wegener et. al. developed from the year 1967, which called a MNOS field effect transistor with programmable threshold voltage ( threshold voltage english ). The charge- trapping memory element was used as charge storage to a programming voltage to the 50 V permanent, until the next programming cycle, change the threshold voltage of the NMOS field effect transistor can. In conventional field-effect transistors, the threshold voltage can be defined only in terms of production is below a fixed component property.