Flash memory#NAND memories

NAND flash indicates a type of flash memory, which is made in the so-called NAND technology. The term " NAND " technique refers to the serial arrangement of the individual memory cells: They comprise a special MOS FETs that are connected as in a NAND gate.

There are four producers of corresponding chips: Samsung ( segment "Samsung Semiconductor " ), Toshiba, IM Flash Technologies is a joint venture of Micron Technology and Intel, as well as in cooperation with Hynix Numonyx. Market Leading manufacturer is the Korean company Samsung, followed by Toshiba, which together produce the majority of all chips.


The space requirement for a flash memory cell in NAND technology is, according to Toshiba only about 2 /5 of the surface that is required for a memory cell in NOR technique.

NAND flashes basically work page and block-oriented. A page consists of an assembly of at least 512 bytes, but this was increased in the course of miniaturization of transistors and associated increase in storage density to 4096 bytes to 8192 bytes. A plurality of pages are grouped into one block. The block size was smaller memory sizes at 16 kb and is now with larger memory blocks on 128 pages ( 512 kB at 4 kB page size ) to 256 pages (2048 KB at 8KB page size ) increased.

Pages can be written only once; further write operations are possible only after a new deletion. Due to the grouping one Deleting a page is only a Clear block possible in which it lies. As in conventional flash memories, which bits can be dumped into the bytes of only from 1 to 0. The reverse path is only accessible via a deletion.

In NAND flashes, it is common that some defect blocks that Bad Blocks, already are known as present at the time of delivery. These are already detected by the manufacturer using specific tests and marked as defective. Later they have to be taken into account by the driver software. Is guaranteed to be the most NAND flash manufacturers, that the first block of a memory module for a given number of write operations is error free. This allows the storage of important initial data as a "Bad block table " at a fixed address, while all other data must be variable in their respective address locations.

In NAND flash memories, each associated with a fix Page Save Page. This was 16 bytes long in smaller blocks, with larger blocks of 64 bytes. In it are stored, among other things by the manufacturer bad block markings or in regular operation at error-free blocks correction data for forward error correction (FEC ) to correct any scanning errors. The Spare pages are firmly coupled with the user data pages: If a page ( ie a block ) deleted, it will be deleted also the associated Save Pages. In practice, this means that as broken highlighted blocks not erased ( formatted ) may be, as this is lost, the error information about bad blocks. Due to this, the NAND Flash device can not be completely deleted via a command, but must block by block in single steps, be except those marked as defective blocks deleted.

The initial bad blocks are determined by the manufacturer under extreme tests, such as extreme temperatures and variable access speeds in the boundary area is determined. Under normal operating conditions, such as at room temperature, these bad blocks do not always work incorrectly.

In NAND flashes can also occur during operation bit errors that must be detected and treated by appropriate error correction procedures. Blocks with such runtime errors must also be added from the NAND Flash controller or the software driver system to the list of bad blocks. The part that is responsible for managing bad blocks is called Bad Block Management System.


In a NAND flash cell can be carried out, the data storage having a different number of voltage levels within the floating gate. With two different voltage levels per cell may be a bit per cell are stored, this NAND cell is referred to as SLC memory cell., Four different voltage levels used to allow two bits per cell can be stored, as is the case with the MLC memory cells. With eight different voltage levels can be three bit per cell NAND store.

The advantage of the SLC memory cells is an increased number of write cycles, and more robust, since in the read operation, only two voltage levels are to be distinguished.

The advantage of the MLC memory cells is a more efficient use of chip area and higher memory density. Disadvantages are the longer access times, and the reduced number of write cycles to the MLC memory cells. This reduction results from the fact that the discrimination between the different voltages is difficult and subject to greater error probabilities by using four or more voltage levels.


The access to the NAND memory is typically a multiplexed Adress-/Datenbus instead of a width of 8 bits. The protocol used is command based. Due to the bus interface used a relatively large software overhead for control is necessary or in hardware as IP core corresponding NAND flash controller for access control are necessary.

In addition, in particular the boot a system is only possible with additional hardware in the form of a NAND Flash controller. A conventional processor with Adress-/Datenbus can not directly address this memory. In NOR Flashes this is not a problem, the firmware of a computer is therefore usually stored in NOR memories. In NAND storing the data on a file system with bad block management system are stored.

Areas of application

NAND flashes are mainly designed for large amounts of memory; They are used in USB sticks, Flash memory cards ( eg, CF and SD cards), SSDs as well as in virtually all based on semiconductor memory MP3 players.


  • Very low price per megabyte
  • High read and write speeds for large data volumes
  • Lower power consumption during programming
  • NAND flashes are available with high storage
  • The small number of signal lines required permits ( in hardware ) cost coupling to controller systems
  • The command- based bus interface allows the use of chips with greater storage capacity without changing the circuit design


  • Compared with NOR save a considerable software effort is required to control NAND memory correctly
  • Due to the type of access used NAND memory can not be used directly as a program memory for microcontroller ( they require a linear addressable memory with random access )
  • For connection to a conventional controller systems glue logic is required.
  • 100,000 to 1,000,000 write-erase cycles in SLC, then the memory is no longer usable.
  • 3000-10000 write-erase cycles of MLC, then the memory is no longer usable.