Floorplan (microelectronics)#Floorplanning

Floorplanning (English for floor plan ) denotes an optimization problem are to be located at the functional groups or components in a system so that there are as short as possible connection, transport or signaling pathways. Plays a major role floorplanning today in the chip design and layout design, where an overall circuit is divided into individually to be designed sub-circuits.

Description

The optimization goal is to minimize the floorplanning of the link, transport or signaling pathways, mostly in order to optimize the rate or size of an electronic circuit. Examples are

• Arrangement of the circuit blocks on a circuit board,
• Arrangement of sub-circuits in an integrated circuit,
• List of machines in a factory for a production sequence ( original origin of the term ) and
• Placement of the shelves and merchandise on the shelves in a retail establishment.

In chip design, a distinction floorplanning in early and late stages of design. After behavioral and structural design guide partitioning and floorplanning a layout synthesis. Key tasks during floorplanning are setting the shapes and arrangement of circuit blocks ( planning of block shapes and positions) and the signal assignment of I / O pins (connections ).

Since many of these tasks are NP-complete and have a large amount of solution, the calculation of optimal solutions is not possible in a reasonable time and there are approximation algorithms and heuristics used.