Hardware description language
May be a hardware description language (English Hardware Description Language HDL) is a formal language with the operations of integrated circuits and their design described and tested in simulations.
Hardware description languages express a temporal behavior and / or a ( spatial ) Circuit structure in normal text. Unlike software - programming syntax and semantics of HDLs include in their notation ways to express temporal sequences and co-existences, as required by hardware. Languages , whose sole characteristic is to reproduce connections of circuits in the form of netlists, are referred to as netlist languages.
Demarcation
Regular ( and incorrectly) the term programming is used synonymously for writing a hardware description. This results from the fact that HDLs represent an executable specification of a particular hardware. A simulation program that provides the basic semantics of the language and the passage of time, the hardware designer provides the ability to model a piece of hardware before being physically prepared. This possibility of execution makes it look as if to use this language to program something. There are HDLs and simulators for modeling in digital and analog technology.
It is possible to semantically describe hardware in a common language such as C , in conjunction with extensive class libraries. Follows this approach SystemC, which currently but is capable of synthesis only in exceptional cases and is primarily used in academia. Normal C also contains, however, no ways to describe a time course, and is therefore not suitable.
Application
One reason for the use of a general HDL is the possibility of automatic generation of netlists for integrated circuits by a synthesis tool. Nor can so easily circuits in programmable devices such as Field Programmable Gate Arrays (FPGAs ) or application specific integrated circuits (ASICs ) can be realized.
For the synthesis of the circuit, the generation of a netlist, typically only a part of speech, based on the syntax and semantics, are suitable. In the field of digital circuit preferably, the logic synthesis is used. The remaining parts of the language are suitable for simpler modeling a test environment for verification of the functionality in simulation programs. An example of a non- synthesis -capable language construct that is the input and output files (file I / O), which is only available in the simulation environment. The detailed scope of what parts of the language are still capable of synthesis depends on the synthesis tools used. So in the early days of logic synthesis digital multiplications were not directly synthesized. The available tools dominate in 2008 as a rule, the direct synthesis of the multiplication operation in hardware.
The following levels of abstraction are used:
- Model of behavior ( behavioral, partly not synthesis capability)
- Register Transfer Level (RTL model, synthesis capability)
- Gate level model ( netlist )
Well-known examples
The first hardware description languages ( to 1977) were ISP ( Instruction Set Processor) from Carnegie Mellon University, and KARL, of the University of Karlsruhe, later further developed at the University of Kaiserslautern. ISP resembled a software programming language, and served description Ein-/Ausgabe-Verhaltens for simulation. Thus, it is hardly used for synthesis. For language KARL and its implementation also included a draft - calculus in support of " VLSI chip floorplanning " and structured hardware design. It also forms the basis of Karl's interactive graphical sister - language ABL, implemented at the research CSELT in Turin, Italy, as a graphical VLSI Design System ABLED in the early 1980s. In the mid-1980s, an EU-funded consortium implemented a complete " VLSI design framework" to KARL and ABL around (). In 1983, the company Data I / O ABEL language in order logic systems and derailleurs (finite state machines ) to describe. Verilog and VHDL are currently among the most widely used languages and have established themselves as industry standards.