Joint Test Action Group

Joint Test Action Group ( JTAG short ) is a commonly used synonym for the IEEE Standard 1149.1, which describes a methodology for testing and debugging of integrated circuits hardware on printed circuit boards. The acronym JTAG points today but on the company JTAG Technologies ( www.jtag.com ), which provides hardware and software for the test according to the IEEE standard. The most prominent and simultaneously implemented first in the JTAG working group process is the Boundary Scan Test IEEE 1149.1. Adding more processes ( 1149.1-1149.8 ), the terms are no longer synonymous, as the description language of the IEEE working group with Boundary Scan Description Language retained the original name.

Purpose of the procedure is to test integrated circuits (ICs ) to function while they are already in their work environment, such as soldered on a circuit board. For this purpose, has a JTAG -compatible IC components that are completely separated in normal operation and thus does not interfere with the function of the component. Only after activation of the function on a particular JTAG pin, the test mode select input, can be influenced by means of these additional components, hardware system and controlled by it. The interface of JTAG to the outside world is implemented as a shift register.

2.4.1 The Instruction Register
2.4.2 The Data Register 2.4.2.1 The BYPASS register
2.4.2.2 The IDCODES register
2.4.2.3 The boundary scan register
2.4.2.4 Additional tabs

Motivation and Development

The late 1970s, the degree of integration of microelectronics was time increased (contemporary complex IC are Intel 4004, Intel 8008 or Zilog Z80 ) that ICs worked in a chip with thousands of flip-flops and registers. The states of these internal flip-flops are no longer accessible with an IC. There was the claim ( the first IC manufacturer itself) that to test the structure of a complex block which gate lines and controllable, to test the function of the states ( all registers and flip-flops ) should be observable. Eichelberger published in 1977 as a designated scan path approach, in which each flip-flop in the IC an additional multiplexer ( transfer gate ) shall be at the entrance. Now In this way, all the flip-flop of the IC can be connected either to a long shift register, each about the state of each flip-flop is observable and controllable from outside.

The JTAG standard created by a consortium of semiconductor manufacturers in 1985 / 86th It has developed a standard which was held in the IEEE 1149.1-1990. With the revision of IEEE 1149.1-1994 is the Boundary Scan Description Language part of the standard. The current version of the standard is IEEE 1149.1-2001 standard test access port and boundary-scan architecture.

Operation

Construction

A JTAG component consists essentially of the following parts:

A Test Access Port (TAP) to the control lines, generally called JTAG port or JTAG interface.
The TAP controller, a state machine, which controls the logic test.
Two shift registers, the " Instruction Register" ( IR ) and the "Data Register" ( DR).

Test Access Port

The Test Access Port (TAP ) consists of five control lines:

Wiring of the whole circuit

A hardware system to multiple taps may be provided, which are chained together. Which is referred to as a " JTAG chain ." It is effective in the control case to a series circuit of the shift registers of the TAP involved, but other circuit pattern defined in the JTAG standard. The TAP controller of the individual TAPs run it in parallel.

TAP controller

The TAP controller is clocked by the TCK and controlled by the TMS line state machine. The TMS line determines into which subsequent state jumped on the next clock. The TAP controller has six stable states, that is, states in which several bars can be left long. These six states are "Test Logic Reset", " Run Test / Idle ," "Shift -DR " and "Shift -IR " and "Pause -DR " and "Pause - IR". In the " Test Logic Reset" is the test logic reset " Run Test / Idle " is used as hibernation or for waiting. The two " Shift" states are able to push the DR or IR shift register. The two " pause" states serve the interruption of shift operations. For all other states will jump on the following clock in another state. When going through each specific control functions are triggered.

Register

An IC having JTAG port has two outwardly register, instruction register ( IR) and the data register ( DR). The Data Register stands for a group of different registers, which are involved in the transmission of user data.

Wherein a shift operation while the TDI input is " pushed " into the first bit of the shift register, the bit of the rearmost shift register is " pushed " to the TDO output. If multiple TAPs connected in series in a JTAG chain, have information that is specific to a particular TAP, be pushed through the shift registers of the other TAPs. Which of the two registers (IR or DR) is inserted depends on whether the TAP controller is in the DR or in the IR path.

The Instruction Register

When a shift operation by the data register ( DR, see below) is performed, is the value of the instruction register to (IR), by means of which of the data registers, the shift operation is performed. Due to the interconnection of the shift register, the instruction registers of all devices in a JTAG chain can only be written together.

The IR has no fixed length, but at least 2 bits must be large. Some microcontrollers, it is 4 bits (eg ARM, Maxim / Dallas DS4550, Renesas SH- microcontroller), with other 5 bits (eg Freescale MPC5554 ) or 8 bits ( eg Infineon C166 ) wide.

Certain values of the IR can be interpreted as a command from TAP upon completion of the shift operation. When reading the Instruction register is often used as a status register.

The Data Register

A data register ( DR), those registers are designated, which are involved in the transmission of user data. On the hardware side, this is often a single shift register, which takes over the duties of the respective JTAG register. Which register is mapped out is determined by the instruction register. Can be understood as a control of a multiplexer which multiplexes the data register to the TDO output. The IEEE 1149.1 standard requires certain registers that must be included in all JTAG -enabled devices. These are the BYPASS, the IDCODES and the boundary scan register.

The BYPASS register

In this data register is a shift register having a bit width. The background is that the data register ( DR ) of all TAPs as the IR can be read and written simultaneously. If only the data register of a single TAP in the " JTAG chain" be read or written, the BYPASS instruction is loaded via the IRs of all other TAPs, so this register is selected. Thus, the latency of the scan chain, which is produced by the sliding operation, can be minimized.

The IDCODES register

At the start of a shift operation through this data register ( DR) an identification number (manufacturer and product type) is loaded into the shift register, which is used to identify the TAP.

The boundary scan register

The individual memory cells of the boundary scan register ( BSR) to allow access to the logic circuits connected to the TAP. This may be required circuits or also represent all in-circuit emulators for special scanning tests. The exact meaning depends on the manufacturer. Similar to a programmable logic controller can be determined by the boundary scan register of the voltage level of all outputs, and the voltage levels of all the inputs are read. This is used for scan test.

Additional tabs

Additional registers can still be defined, for example, provide a debug or programming available over the three prescribed data register also. For instance, features in the case of the TAP ARMv5 three special registers to be addressed as a data register ( DR).

In order to use the JTAG port of an IC, it is necessary to know their construction and registers contained exactly. This is described in a BSDL file provided by the manufacturer.

Other applications

Meanwhile JTAG is increasingly used to configure FPGAs and CPLDs as well as for programming and debugging of microcontrollers. Parallel programmable memory such as flash memory, which are directly connected to an IC having JTAG port, therefore, can be reprogrammed in the assembled state, because the IC memory chip can emulate a programming device. To replace such programming data often serves the Serial Vector Format ( SVF ).

Extensions

IEEE Standard 1149.1 has now been provided with a number of extensions. These are:

A further extension of the JTAG standard, becoming specifically for programming JTAG -enabled modules under the name IEEE Std 1532-2002: IEEE Standard for In-System Configuration of Programmable Devices adopted. A this -standard block has some additional registers are provided for its programming.

Debugger Integrated device manufacturer Finite-state machine ARM architecture Freescale Semiconductor Analogsignal Digital Object Identifier

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