Motorola 68040

The Motorola 68040 is a 32 -bit microprocessor of the Motorola company. He has in the full version two integrated MMUs ( according to the Harvard architecture ) and the Motorola 68881/68882 almost completely compatible FPU, and a Level 1 cache of 4 KiB each for data and instructions. Thus it is performing in integer range about twice as much as an equally clocked Motorola 68030th The integrated FPU is more than twice as efficient as a Motorola 68882nd you follows the IEEE 754 floating point standard and contains no logic for trigonometric functions, this must be emulated in software.

History

The Motorola 68040 was the early 1990s, a popular microprocessor for upscale personal computers and workstations, installed among other things in the newer versions of NeXTcube and the Next station of the company NeXT, Apple Macintosh Quadra, and Macintosh Performa, HP Apollo 400 series and Amiga 4000.

Motorola could not keep the delivery date for the first 68040; so some manufacturers have had to delay their products also or as otherwise manage HP: The HP Apollo 400t was already announced, only the 68040 processor was still lacking in numbers. The engineers quickly developed a daughterboard with 68040 pin -compatible port on a Motorola 68030 Motorola 68882 sat together at 50 MHz and 128 KiB L2 cache. The reputation of Motorola in the industry was not conducive to this, at the end customer, however, was the 68040 fans for its excellent value for money.

After the 68040, many computer vendors did not rise to the successor Motorola 68060, but switched directly to other processor platforms, such as PA -RISC in the case of HP and Apple PowerPC.

A variant of the 68040 is the Motorola 68LC040 without FPU. Another variant is the Motorola 68EC040 without PMMU and FPU, with a rudimentary memory management via four access control register.

Variants

  • 68040 - complete CPU with FPU and MMU
  • 68LC040 - disabled FPU, MMU present
  • 68EC040 - FPU and MMU disabled
  • 68040V - "Low Voltage" version of the 68LC040

Technical Features

  • Vcore 5 V
  • Vcore 3.3V ( 68040V )
  • I / O 5 V
  • 4 KiB DCache
  • 4 KiB ICache
  • Entry 64 ATC MMU Buffer (4- way set associative )
  • 8 address registers
  • 8 data registers
  • 2 Status Register
  • 8 Floating Point Data registers, each 80 bits wide
  • 1 Floating Point Instruction Register
  • 1 Floating Point Status Register
  • 1 Floating Point Control Register
  • ~ 29 MIPS @ 40 MHz ( manufacturer's specification of 44 Mips is rather unrealistic )
  • ~ 11 MFlops @ 40 MHz
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