PowerPC e200

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The e200 core belongs to the class of 32-bit RISC processors from the PowerPC family. It was designed by Freescale mainly for automotive and industrial control systems and provides an SoC at a speed of up to 600 MHz and is therefore suitable for embedded applications.

The e200 is derived from the MPC5xx family and used the Power ISA v.2.03 and the older book E specifications. The e200 SoC follow the MPC55xx and MPC56xx/JPC56x naming scheme.

From April 2007, Freescale and IPextreme opened the design of the e200 for licensing purposes and productions by other companies.

Freescale and Continental AG to develop a triple-core e200 for electronically assisted braking systems in automobiles.

Cores

The e200 family consists of six different nuclei, starting from very simple to highly complex cores for specific applications.

E200z0

The e200z0 is the simplest version of the e200 core. It has a 4-stage non- issue superscalar instruction pipeline, the instructions linear ( in-order execution ) executes. There is no MMU or FPU present. The e200z0 uses the specification VLE (16-bit version of the 32-bit Book E specification ) and achieved an up to 30% higher code density. As a single-channel bus AMBA bus is applied.

E200z1

The e200z1 has a 4-stage non- issue superscalar instruction pipeline with a unit for jump predictions ( branch prediction) and an 8 -entry MMU. FPU is not present. The e200z1 can all 32-bit Power ISA and VLE process commands and uses a dual-channel 32-bit AMBA bus.

E200z3

The e200z3 is a e200z1 core extended by a 16 -entry MMU and FPU SIMD enabled. He can also use all commands of the Power ISA and VLE specification but has, in contrast to e200z1 a two-channel 64-bit AMBA bus.

E200z4

The e200z4 has a 5 -stage 2-way superscalar instruction pipeline with a unit for jump predictions ( branch prediction), a 32 -entry MMU, a SIMD -capable FPU and a combined 16 KiB large L1 cache ( Von Neumann architecture ). He uses as his predecessor all the commands of the Power ISA and the VLE specification and is connected via a two-channel AMBA bus.

E200z6

The e200z6 features a 7-stage non- issue superscalar instruction pipeline with a unit for jump predictions ( branch prediction), a 32 -entry MMU, FPU and SIMD enabled a combined 32 KiB large L1 cache. He uses as his predecessor all the commands of the Power ISA and the VLE specification and is connected via a two-channel AMBA bus.

E200z7

The e200z7 has a 10 -stage 2-way superscalar instruction pipeline with a unit for jump predictions ( branch prediction), a 32 -entry MMU, FPU and SIMD enabled a combined 32 KiB large L1 cache. Just like its predecessor, it uses all the commands of the Power ISA and the VLE specification and is also connected via a two-channel AMBA bus.