Programmable Array Logic

( Abbreviated PAL) Programmable Array Logic are electronic semiconductor components in the field of digital technology that obtained by programming a logical link structure of the input signals to the output signals. They were developed in 1978 by the company Monolithic Memories Inc. ( MMI) and produced in the following years.

General

PALs are special cases of PLAs (Programmable Logic Arrays ) and characterized that only you AND array is programmable. PALs are only writable once, because the links are on the chip as part of the programming process produced by " burning through connections," the so-called antifuse technology.

As a further development of PALs devices first came through the Lattice Semiconductor Corporation rewritable Generic Array Logic ( GAL for short ) on the market. They consist of a programmable AND matrix and a hard-wired OR array. In contrast to the PAL are electrically writable and either by UV light ( EPLD ) or electrically ( EEPLD ) deleted, thereby reprogramming is possible.

The term GAL is a trademark of Lattice, so there are some companies who call these blocks with their original name under license, and other companies, which have renamed these blocks ( in AMD, for example, under the name PALCE ) - this differs from the programming algorithm but not the pin assignment and function.

The designation is in the pattern of what it is for a logic module, and provides information about its properties. A GAL16V8 is a Gal - block with 16 matrix inputs for the logic array, the output type v (variable architecture) and has eight outputs. Then comes to a minus the gate propagation delay in ns and other information about operating temperatures and the chip housing.

GAL devices have three different operating modes, which are defined by two Architekturbits during programming. A third bit is set for the function outputs, whether they are intended to function as an input or output ( AC1 ( n), n = pin number ). This means that in general, any output can be used as an input. The Simple mode (SYN = 1, AC0 = 0) allows the use of the GAL module as a simple logic gates, with linkage of the AND - OR - blocks with subsequent blocks. The complex mode ( SYN = 1, AC0 = 1) can be the multiplexing using tristate outputs to, and the last of the modes, the mode register allows the interconnection of logic gates having registers through integrated D flip-flop. This allows you to build even smaller complex circuits without having to constantly expand the circuits further external logic devices.

Since the mid- 1990s PALs and GALs are rarely used in newly developed circuits and have been almost completely superseded by Complex Programmable Logic Devices ( CPLDs ). CPLDs have no restrictions on the use of UND-/ODER-Matrizen at the entrance, are electronically programmable and erasable, are as Field Programmable Gate Arrays ( FPGAs) in uniform hardware programming languages, such as VHDL, programmable and include beyond a certain number of registers.