Strain engineering

The English term dual stress liner (DSL ) called in semiconductor technology, a process for the preparation of strained silicon (English strained silicon ) for p- and n- channel MOSFETs in silicon-on -insulator technologies. The IBM-developed method comes by the technology exchange agreements is / was used among others in AMD / Globalfoundries and Chartered Semiconductor Manufacturing.

In this case, after the production of the MOSFET silicon nitride ( Si3N4) is deposited over the devices. Depending on the process conditions, this silicon nitride layer acts compressible or relaxing of the underlying source and drain regions. These local tensions affect complementary to the channel region between the source and drain regions of, ie compressed source and drain regions lead to a stretched silicon in the channel region, and vice versa. Technologically, both types are used by tensions: Since the electron mobility increases in the relaxed ( tensilem ) silicon, such areas are suitable for channel n- MOSFETs; In contrast, compressible silicon leads to increased hole mobility, which is exploited in p- MOSFETs.

The advantages of DSL technology lie in their compatibility with propagated by IBM and AMD SOI technology and the fact that in contrast to the strain- transfer process used by Intel, the electronic properties of p- and n-channel MOSFETs are equally improved.

• Semiconductor Technology