SystemVerilog

SystemVerilog is the first hardware description and verification language (English Hardware Description and Verification Language, abbreviated HDVL ). It offers possibilities for the design and verification of digital circuits. SystemVerilog was developed by Accellera and is an extension of the IEEE 1364-2001 Verilog HDL. Here SystemVerilog but operates at a higher level of abstraction than Verilog - 2001.

History

Verilog - 1995 has for many years on the market and is next to the most used VHDL hardware description linguistic fields The IEEE has expanded the features of Verilog 1995, they were classified in Verilog -2001. However, this language scope is still insufficient for an efficient verification of register transfer level (RTL) described digital hardware. Therefore, the developers have often other languages, such as "e", or test Vera builder used. Since SystemVerilog is both a hardware description language as well as a verification language, both parts of the language must be considered separately. The hardware description aspect of SystemVerilog is a consistent further development of the Verilog -2001 standard. It is different from the verification aspect of SystemVerilog. This part of speech was significantly influenced by Synopsys Vera, according to its object-oriented syntax of Verilog -2001 stands out clearly from.

Standardizing SystemVerilog carried out in several stages. In June 2002 was released SystemVerilog 3.0, in May 2003, version 3.1, and finally the 3.1a version in April 2004. With the development of SystemVerilog 3.1, the main verification techniques should be integrated into SystemVerilog. Since 2005, SystemVerilog is maintained as IEEE Standard 1800. 2009, the standard was extended and that of IEEE 1364 absorbed therein. 2013, the next one, rather minor revision was published under the name IEEE 1800-2012.

General information about SystemVerilog

Some of the features of SystemVerilog:

  • Data types similar to 'C': int, typedef, struct, union, enum
  • Dynamic data types: struct, classes, "dynamic cues ", "dynamic arrays"
  • New operators and "built-in methods"
  • Advanced program control: foreach, return, break, continue
  • Semaphores, mailboxes, and "events"
  • Classes for object-oriented programming
  • " Assertions "
  • Code set cover analysis
  • VPI Extensions ( Verilog Procedural Interface)

The IEEE has SystemVerilog standardized as IEEE Standard 1800. Anyone with C experience will quickly feel familiar with SystemVerilog. Since SystemVerilog has many bonds to C , it is someone who has never dealt with object-oriented programming, difficult to use SystemVerilog in full.

SystemVerilog is composed of three parts: the long been known and standardized Verilog, a second part that defines the writing of assertions in SystemVerilog, and the object-oriented part, which is used exclusively for verification.

Operation

Example, the use of strings and screen output

/ / This is a SystemVerilog comment. string sv = " SystemVerilog "; string s; s = { sv, "", " 's real simple ." }; $ display ("% s \ n", s); / / Display output: " SystemVerilog 's real simple. " s = {s, "- tried it once! "}; $ display ("% s \ n", s); / / Display output: ". SystemVerilog is really easy - try it out! " see also

Institute of Electrical and Electronics Engineers
758593
de