MESI protocol

MESI (Modified Exclusive Shared Invalid ) is a protocol for maintaining cache coherency in memory- coupled multiprocessor systems. The MESI protocol was first published by researchers at the University of Illinois. It is also often referred to as Illinois protocol.

Since memory coupled multiprocessor systems, each processor has a cache must be set if any of the cache or the main memory contains the current value of a date. A system is called cache- coherent if it guarantees can obtain the current value of a date at all times, even if it is in another cache.

In the MESI protocol, each cache line are assigned to two status bits, is described by one of the following four states:

The transitions between these four states can now be triggered in two ways: Either

• Directly by writing or reading the data from the program
• Indirectly ( bus snooping ) through the eavesdropping of the actions of another processor on the bus through the cache. Here, a cache uses the following control signals:

A processor may access from or to a single address in the storage system. Accordingly, solving read and write operations of a processor of bus transactions. In the MESI protocol, there are the following bus transactions:

The read and write operations, as well as the bus transactions by directly and indirectly generated determine the behavior of the state machine, which is defined by the MESI protocol ( see figure).

Example

Let us assume a computer system having two processors, two caches, each with a cache line and shared main memory, which uses the MESI cache coherency protocol.

Main memory cache A cache B -------------------------------------     Date_1 - Now A processor loads the Date 1, then this is stored in the cache. This cache A cache signaled to B that date 1 is loaded. Because cache B has no entry for date 1, this indicates nothing. A cache can therefore select date 1 as Exclusive ( unmodified ).

Main memory cache A cache B -------------------------------------     Date_1 E Date_1 - Then required processor B, the date 1 and loads it. It signaled Cache B that date 1 is loaded. Because cache A already has an entry for date 1, he signaled during which both shared caches and mark their entry as shared ( unmodified ).

Main memory cache A cache B --------------------------------------     Date_1 S Date_1 S Date_1 A processor has completed its work with date 1 and then change its value. Since Date 1 with Shared ( unmodified ) is selected, cache A signaled when changing the entry Invalidate, whereupon Cache B marks the entry with Invalid. A cache changes the value of date 1 and date marked 1 then with ( exclusive) Modified since after Invalidate signal no other cache has this value of stock.

Main memory cache A cache B ---------------------------------------     Date_1 M Date_1 ' I Date_1 Now processor B would like to work with date 1. So he asks of cache B the value. However, cache B has these not available, since a marked as invalid entry is treated as a non-existent entry. So cache B tries to load date 1 from the main memory. In this case, it signals at the cache A, that he wants to do this. A cache but recognizes that the value in main memory is out of date, because it has itself an entry with date 1 and the mark ( exclusive) Modified. So A cache must prevent the wrong value is used from the main memory. He immediately sends the retry signal. Cache B registers this and aborts the loading process. Cache A to give sufficient time to Cache B waits for a short period of time. Meanwhile cache writes the current date A 1 in the main memory and then sets its own value on shared.

Main memory cache A cache B ---------------------------------------     Date_1 ' S Date_1 ' I Date_1 After the end of the waiting period would now like to cache B finally have date 1 and reads this from the main memory. Cache A registers the read process signals and both shared caches have entered the current date 1 with the mark shared ( unmodified ).

Main memory cache A cache B ---------------------------------------     Date_1 ' S Date_1 ' S Date_1 ' A further development of the MESI protocol is the MOESI protocol.