Transmeta Efficeon

Developed under the codename Astro Efficeon is a particularly low-power processor family, the company Transmeta, which should be, especially for embedded systems, notebook PCs, low-noise workstation, in not requiring an active cooling system used.

The 256 -bit processor sets as its predecessor Crusoe on the code - morphing technique and the VLIW architecture. The efficiency of the code - morphing, however, was significantly improved. So far, this technique emulates the x86 processor architecture, including Intel SSE2 instruction set extension. Theoretically, however, other architectures could be emulated.

Model data

TM8300

  • L1 - Cache: 64 128 KB ( data instructions )
  • L2 cache: 512 KB with processor clock
  • MMX, SSE, SSE2, LongRun! 2
  • VLIW with code - morphing technique
  • Integrated North Bridge in CPU
  • Packaging: 783 Pin BGA

TM8500

  • L1 - Cache: 64 128 KB ( data instructions )
  • L2 cache: 512 KB with processor clock
  • MMX, SSE, SSE2, LongRun! 2, NX bit
  • Integrated North Bridge in CPU
  • Packaging: 783 Pin BGA

TM8600/TM8620

  • L1 - Cache: 64 128 KB ( data instructions )
  • L2 cache: 1024 KB with processor clock
  • MMX, SSE, SSE2, LongRun! 2
  • VLIW with code - morphing technique
  • Integrated North Bridge in CPU
  • Packaging: 783 Pin BGA ( TM8600 )
  • 592 Pin BGA ( TM8620 )

TM8800/TM8820

  • L1 - Cache: 64 128 KB ( data instructions )
  • L2 cache: 1024 KB with processor clock
  • MMX, SSE, SSE2, SSE3, LongRun! 2, NX bit
  • VLIW with code - morphing technique
  • Integrated North Bridge in CPU
  • Packaging: 783 Pin BGA ( TM8800 )
  • 592 Pin BGA ( TM8820 )
Transmeta Crusoe Northbridge (computing) TSMC Fujitsu
256472
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