Dynamic Random Access Memory

Dynamic Random Access Memory (DRAM ), or the half- Germanized term dynamic RAM, is a technology for an electronic memory device having random access memory ( Random Access Memory, RAM), which is mainly used in computers, but also in other electronic devices such as printers will apply. The storage element is a capacitor, which is either charged or discharged. Via a switching transistor it is available and either read or written with new content. The memory content is volatile ( volatile ), ie, the stored information is lost in the absence of operating voltage or later to refresh.

• 3.1 Initial state
• 3.2 Activation of a memory line
• 3.3 Reading Data
• 3.4 Writing data
• 3.5 Deactivation of a memory line
• 3.6 Timing parameters of the internal processes 3.6.1 tRCD
• 3.6.2 CL
• 3.6.3 tRAS
• 3.6.4 tRP
• 3.6.5 tRC

• 4.1 Address Multiplex 4.1.1 addressing 4.1.1.1 RAS
• 4.1.1.2 CAS

• 7.1 memory
• 7.2 Special Applications

Introduction

A hallmark of the DRAM is the combination of a very high data density on a small chip area, combined with very cheap cost. He is therefore mainly used in applications where large amounts of memory at medium data rate per pin of 100-1600 Mbit / s have to be provided.

This advantage of the DRAM compared to the SRAM is offset by the disadvantage that the charge stored in the capacitor and thus the information stored volatilized due to leakage currents over time if not periodically refreshed again. This is normally required at intervals of a few milliseconds. The refreshing of the memory is accomplished by lines. To a memory line is transferred in one step in a on-chip line buffer and then rewritten back into the memory row amplified respectively. Therefore, the name comes "dynamic". In static memories such as SRAM can contrast all signals to stop, without any data loss occurs. The refresh of the DRAM also consumed even at rest, a certain amount of energy. Therefore, it is preferable in applications which require a low quiescent current, SRAM.

Charge does not volatilize under certain conditions ( or simply by manufacturing tolerances permitting) within milliseconds, but still may be seconds to minutes in the memory cells. Researchers at Princeton University to forensic data even read right after a cold start succeeded. The components are specified for safety's sake always with the guaranteed worst-case value, ie, the shortest occurring hold time.

The manufacturer of memory continuously try to reduce the energy demand by the losses are minimized by load as well as leakage currents. Both depend on the supply voltage which is for DDR2 SDRAM at 1.8 volts, while DDR SDRAM will be supplied with 2.5 volts. In the introduced in 2007 DDR3 - SDRAM, the voltage to 1.5 volts was lowered.

A DRAM is performed either as a standalone or as an integrated circuit memory cell part of a larger chips.

The "random " in this case is random access memory for random access to the memory contents of the individual memory cells and, in contrast to the sequential access, such as when ( in hardware organized) FIFO or LIFO memories.

Construction

A DRAM is not in the article semiconductor memory simplifies shown from a single two-dimensional matrix. Instead, the memory cells are arranged and wired on the surface of a die is divided into a sophisticated hierarchical structure. While the inner structure is built specific to the manufacturer, the externally visible logical structure of the industry body JEDEC is normalized. This ensures that it is possible chips from different manufacturers and of different sizes respond following the same scheme.

Construction of a memory cell

The structure of a single DRAM memory cell is very simple, it only consists of a capacitor and a transistor. Today, one uses a MOS field effect transistor. The information is stored as electric charge in the capacitor. Each memory cell stores one bit. While in the past mostly found in planar capacitors using, currently two other technologies:

• In the (English stack) stack technology, the capacitor is built up over the transistor.
• In trench technology (English trench ) of the capacitor by etching a 5-10 micrometer deep hole ( or trench ) is formed into the substrate.

• Schematic structure of the fundamental technologies for DRAM cell ( cross-sections )

Stack Technology

Grave technology with poly -Si plate

The drawn in the figure beside upper connection is either charged to the bit line voltage VBL or discharged ( 0 V). The lower connection of all capacitors is commonly connected to a voltage source that ideally a voltage of VPl = 1/2 · VBL has. This allows the maximum field strength in the dielectric of the capacitor in half.

The transistors ( also called select transistor ) is used as a switch for reading and writing the information from the cell. For this purpose, a positive voltage VWL on the word line (English word line ) to the gate terminal "G" of the n- MOS transistor. Characterized a conductive connection between the source ("S ") and the drain regions ("D" ) is produced which connects the cell capacitor to the bit line ( bit line Sheet ). The substrate terminal "B" (bulk) of the transistor is connected to either the ground potential or at a slightly negative SpannungVSub for suppressing leakage currents.

By their very simple structure, the memory cells need very little chip area. The construction-related size of a memory cell is like as a multiple of the square surface F ² the smallest manufacturable structure length ( " minimum feature size " or abbreviated F) stated: A DRAM cell needs today 6 or 8 F ², while a SRAM cell requires more than 100 F ². Therefore, a DRAM store for a given chip size, a much larger number of bits. This results in much lower cost per bit than the SRAM. Under the usual today electronic memory types, only the NAND flash memory has a smaller cell at about 4.5 Q ² ( R ² and 2.2 per-bit multilevel cells).

Construction of a memory line (" Page " )

By connecting another memory cells to a word line to obtain a memory line, commonly referred to as Page (English page ) is referred to. The characteristic feature of a line is the property that all its stored content to spend their cells ( shown in red ) in the activation of a word line at the same time on their associated bit line ( shown in blue ). A typical page size is 1 Ki, Ki 2, Ki 4 (...) cells.

Structure of a cell array

The memory cells are connected in a matrix arrangement: ' word lines ' connect all the gates of select transistors in a row, bit lines connect all drain regions of the select transistors of a column.

At the lower edge of the matrix, the bit lines to the (primary) Schreib-/Lese-Verstärkern (English sense amplifier ) are connected. Since they have to fit into the tight grid of the cell array, they are constructed in the simplest form as two against coupled CMOS inverters only four transistors. Your supply voltage is just equal to the bit line voltage VBL. In addition to its function as an amplifier of the read cell signal they do not have the side effect that their structure corresponds to that of a simple static memory ( Latch). The primary sense amplifier thus simultaneously serves as a memory of a complete line of memory.

The drawn through the sense amplifier switches are in the inactive state for precharging the bit lines to a level of ½ · VBL, which now represents the mean value of the voltage of a aufgeladenenen and a discharged cell.

On a memory chip, a plurality of memory arrays in a contiguous memory region are connected, the chip is so (transparent to the outside) divided internally into sub-matrices. Here, all data lines depending on the design led to a single data pin to the outside or to 4, 8 (rare), distributed 16 or 32 ( DRAM for graphics applications ) data pins. This is the data width of each DRAM chip. Depending on its value you need, for example, 8, 2 or 1 chip ( s ) for a data bus width of 8 bits or four times of that for 32-bit and eight times for 64 -bit.

Address decoding

The diagram above shows the basic structure adjacent the address decoding for a single cell array. The row address is supplied via n address lines to the row decoder. This selects its attached 2n word lines from just a single and activates them by raising their potential to the word line voltage VWL. The resulting activated in the cell field memory line provides its data content now on the bit lines. The resulting signal is amplified by the (primary) sense amplifiers, and stored simultaneously written back into the cell.

The decoding of the column address and the selection of the data to be read is a two step process. In a first step, the m address lines of the column address are supplied to the column decoder. This selects one of the column select lines usually 2m connected and activates them. Thus k bit lines are selected at a time depending on the width of the memory. In a second step, the column selection will be connected, this sub- set of k bit lines in the set of bit lines with a total of k · 2 m to k data lines in the block toward the outside world. These are finally by another write amplifiers (not shown) reinforced.

In order to limit the crosstalk between adjacent memory cells and their supply lines, the addresses are usually scrambled in decoding, after a standardized rule so that they are not be found again in order of binary significance in the physical arrangement.

Internal processes

Initial state

• In the resting state of a DRAM, the word line is at a low potential ( UWL = 0 V). The cell transistors are thus non-conductive, the charge stored in the capacitors remains - apart from unwanted leakage currents - get.
• Both in the diagram of the cell array through the sense amplifiers outlined switches are closed. Through the two bit lines which are commonly connected to a sense amplifier is maintained at the same potential ( ½ * UBL ).
• The power supply of the sense amplifier ( UBL ) is switched off.

Activation of a memory line

• From the passed in an Activate bank and row address (see diagrams for "Burst Read" access) is first determined in which bank and to what memory block is the specified line.
• The switch to ' Bitleitungsvorladung ' to be opened. The hitherto charged to half bitline bit lines are so disconnected from any power source.
• To the word line a positive voltage is applied. The transistors of the cell array are thus conductive. The long word lines, this process may take several nanoseconds, and is thus one of the reasons for the " slowness " of a DRAM.
• It takes place a charge transfer between the cell capacitor and one of the two bit lines connected to a sense amplifier. At the end of the charge exchange cell and the bit line have a voltage of

• The end of this Umladungsvorganges the supply voltage ( UBL ) is switched to the primary sense amplifiers. These begin with the amplification of the small voltage difference between two bit lines and invite one of them to UBL and will discharge the other to 0 V.

Read data

• To read data then the column address must be decoded by the column decoder.
• The corresponding to the column address column select line ( engl. column select line CSL) is activated and connects one or more bit lines at the output of the primary sense amplifier data lines that lead out of the cell array. Due to the length of the data lines, the data have to be reinforced with a (secondary) sense amplifiers at the edge of the cell array again.
• The read data is read in parallel into a shift register, there with the external clock (clock ) synchronization and output increased.

Writing data

• The written into the DRAM data are nearly the same time read the column address.
• The column address is decoded by the column decoder and the corresponding column selection line is activated. Characterized the connection between a data line and a bit line is restored.
• Parallel to decoding the column address take the write data to the column selection block and will be continued to the bit lines. The (weak) primary sense amplifier will be overwritten and now assume a corresponding write data state.
• The sense amplifier now support the unloading of the bit lines and the storage capacitors in the cell array.

Deactivation of a memory line

• The word line voltage is reduced to 0 V or a slightly negative value. Thus, the cell transistors are non-conductive and couple the cell capacitors of the bit lines from.
• The power supply of the sense amplifiers can now be turned off.
• The bit lines connecting the two switches for Bitleitungsvorladung are closed. This raises the bit lines again the initial state (U = ½ UBL ).

Timing parameters of the internal processes

TRCD

The parameter tRCD (RAS -to -CAS delay, row -to -column delay) describes in a DRAM, the time after the activation of a word line ( activate ) must be passed before a read command (read ) may be sent. Said parameter is due to the fact that the amplification of the bit line and the write-back the contents of the cell must be finished before the bit lines may be connected to the data lines.

CL

See also: Column Address Strobe Latency

TRAS

The parameters tRAS (RAS pulse width, Active Command Period, Bank Active Time) describes the time that must elapse after the activation of a line (or a line in a bank ) before a command to disable the line, ( precharge, Close the bank) may be sent. The parameter is given by the fact that the gain of the bit line and the write-back of the information in the cell must be fully completed, before the word line may be deactivated. i.e., the smaller the better.

TRP

The " tRP " parameter (" Row Precharge Time " ) describes the time that must elapse after a precharge command at least, before a new command to activate a line must be sent in the same bank. This time is defined by the condition that all voltages in the cell array (word line voltage, the supply voltage of the sense amplifier ) are turned off and the voltages of all the lines ( in particular those of the bit lines ) are back to their initial level.

TRC

The " tRC " ( " Row Cycle Time" ) parameter describes the length of time in the same bank must be elapsed between two consecutive activations of any two rows. The value corresponds largely to the sum of the parameters tRAS and tRP, and thus describes the minimum necessary time to refresh a memory line.

DRAM specific properties

Address multiplexing

Addressing

The address lines of a DRAM are usually multiplexed, that is, there are only about half as many physically be as required in total. ( On the other hand is usually performed at higher speed SRAMs order the complete address bus on pins so that they can be accessed in a single operation. )

Asynchronous DRAM ( EDO, FPM ) having two input pins RAS ( Row Address Select / Strobe) and CAS ( Column Address Select / strobe) in order to define the use of the address lines: at a falling edge of RAS, the voltage applied to the address lines of address as row address interpreted, on the falling edge of CAS is interpreted as a column address.

RAS

Row Address Strobe, this control signal is applied during a valid row address. The memory device stores this address into a buffer.

CAS

Column Address Select or Column Address Strobe, this control signal is applied during a valid column address. The memory device stores this address into a buffer.

Synchronous DRAM (SDRAM, DDR SDRAM) also have the control inputs RAS and CAS, but they have wasted their immediate function. The combination of all control signals ( CKE, RAS, CAS, WE, CS) Instead, with synchronous DRAMs evaluated at rising clock edge in order to decide whether and in what form the signals must be interpreted on the address lines.

The advantage of the savings of the external address lines is offset by an apparent disadvantage in the form of delayed availability of the column address. The column address is required but only after decoding the row address, the activation of a word line and bit line signal of the review. However, this internal process takes about 15 ns, so that the column address delay resulting from reducing.

Burst

In the adjacent images, respectively, a read access is illustrated in the so-called burst mode as is used in the BEDO DRAM for an asynchronous and a synchronous DRAM. The characteristic element of a burst access ( reading or writing ) is the immediate succession of data ( Data1, ..., Data4 ). The data belong to the same row of the cell array, thereby having the same row address (English row), but different column addresses ( Col1, ..., Col4 ). The time period required for the provision of the next data bits within the bursts is very small compared with the length of time for the provision of the first data is measured from the activation of the row.

While asynchronous DRAMs still all column addresses are specified within the burst had ( col1, ..., Col4 ) is specified for synchronous DRAMs (SDR, DDR), only the start address. The column addresses needed for the remainder of the burst are then generated by an internal counter.

The high data rate within a burst is explained by the need to access to the sense amplifier within a burst only read ( or write). The 2 CMOS inverters (4 transistors) built sense amplifier comply with the basic structure of the cell of a static RAM ( see adjacent diagrams). The provision of the next burst data bits Thus, only the column address is to be decoded, and to activate the corresponding column selection line ( this corresponds to the connection lines to the gate terminal of the transistors M5 and M6 a SRAM cell).

Refresh

The necessary at short intervals refresh (of English. Refresh, filter, freshen up ') of the memory content is generally referred to with the English term refresh. The need arises from the occurrence of undesired leakage currents, which modify the amount of charge stored in the capacitors. The leakage currents have an exponential temperature dependence: the time after which the contents of a memory cell can not be accurately assessed ( retention time ), each cut in half when the temperature increases by 15 ° to 20 ° C. Commercially available DRAMs usually have a prescribed refresh period of 32 ms or 64 ms.

Technically, the primary sense amplifiers are to ( see figure above) equipped with a latch register function in the memory chip. They are implemented as SRAM cells, so as flip-flops. If a particular line (german page, dt page ) is selected, the entire row is copied into the latches of the sense amplifier. Since the outputs of the amplifier are simultaneously connected with the inputs, the amplified signals are directly restored back into the dynamic memory cells of the selected row, they are refreshed with it.

There are various methods of this refresh control:

Depending on the circuit environment has to be interrupted for the refresh of normal operation, for example, the refresh can be triggered in a regularly called interrupt routine. You can, for example, with its own counter variable simply read any memory cell in each row and thus refresh this line. On the other hand, there are situations (especially in video stores), in which the entire memory area is accessed anyway at short intervals, so that no separate refresh operation must take place. Some microprocessors such as the Z80 or current processor chipsets do the refresh automatically.

Bank

Prior to the introduction of synchronous DRAM, a memory controller had to wait for the information to an activated line were written back and the associated word line was deactivated. There was only one line in the DRAM be enabled. Since the length of a complete write or read cycle (row cycle time, tRC ) was about 80 ns, the access to data of different lines was quite time consuming.

With the introduction of synchronous DRAMs were initially 2 (16 MiB SDRAM), then introduced four (64 MiB SDRAM, DDR-SDRAM ), 8 ( DDR-3 SDRAM) or even 16 and 32 (RDRAM ) memory banks. Memory banks are distinguished in that they each have their own address register and sense amplifier, so that could be enabled on a per bank a row now. The simultaneous operation of multiple banks can avoid high latencies, because while a bank is currently providing data, the memory controller must already send addresses for another bank.

Prefetch

In comparison with an SRAM significantly lower speed of a DRAM is due to the structure and operation of the DRAM. ( Long word lines need to be recharged, a read-out cell can their charge slowly spend on the bit line, the read contents must be reviewed and rewritten. ) Shortening of these times is in fact generally via an internally modified structure possible, but the storage density would decrease and so that the space requirement and thus the production cost increase.

Instead, a trick is used to increase the external data transfer rate without having to increase the internal velocity. In the so-called pre-fetching data from a plurality of column addresses per addressing read and written in a parallel-to- serial converter (shift register). From this buffer the data with the higher ( external ) are output clock rate. This also introduced with synchronous DRAMs data bursts, and in particular their respective minimum burst length to explain ( it just corresponds to the length of the shift register used as a parallel -to-serial converter and thus the prefetch factor):

• The SDR - SDRAM ( SDR single data rate) is read per read request one bit of data per data pin: prefetch = 1
• The DDR SDRAM per read request 2 data bits per data pin can be read and displayed in a data burst of length 2: prefetch = 2
• The DDR2 SDRAM per read request 4 data bits per data pin can be read and displayed in a data burst of length 4: prefetch = 4
• The DDR3 SDRAM per read request 8 bits of data per data pin can be read and displayed in a data burst of length 8: prefetch = 8

The same applies to the writing of the DRAM.

Redundancy

With the increase of the storage density, i.e. the number of storage cells per chip, the probability increases that at least one memory cell has a malfunction. To increase the yield of functional DRAMs during production, so-called redundant elements are integrated in the chip design. It is an additional row and column lines with corresponding memory cells. If now in the production final test detected a defective memory cell, then the affected word or row line is disabled. Takes its place one (or more ) words or row line from the set of otherwise unused redundant elements.

To permanently save this configuration change in DRAM, it requires a permanent circuit modification. Two methods are currently in use:

• Using a focused laser pulse corresponding contacts are prepared in the decoding circuits of the row or column address evaporated ( laser fuse ).
• Using an electrical surge pulse will either open electrical contacts ( e -fuse ) or ( for example, by disrupting a thin insulating layer) is closed ( anti- e -fuse ).

In either case, these permanent changes are used to program the address of the line to be replaced and the address of the redundant line to be used therefor.

The number of the built- in DRAM design redundant elements is only about 1%, surprisingly low. With a higher proportion of redundant elements while larger defects ( memory blocks ) can be repaired, but this would be associated with disadvantages. Usually, reduces the number of defects on a memory device with progressive improvement of the manufacturing process. The no longer needed redundant elements would only chip area demand (increased cost ) to achieve without an appreciable increase in the yield.

The use of redundant elements for the correction of defective memory cells may not be (FEC ) can be mixed with the active error correction based on parity bits or error correcting codes. The error correction redundant elements described here are performed usually once before the delivery of the memory device to the client. Subsequent errors (degradation of the component or transmission fault in the system ) can thus not be eliminated.

See also: Memory Module: ECC

Modules

Often all memory modules with the actual memory block to be confused. The distinction is also reflected in the size marking: DIMMs do you measure in Mebi or gibibyte ( GiB or MiB ), each chip on the DIMM module in contrast Mebi or Gibibit. Through advances in manufacturing technology, manufacturers can accommodate more and more memory cells on the individual chips so that 512 - Mibit devices are readily available. Only by the interconnection of the individual SDRAM chips results in a memory device, which corresponds to the standard.

History

The first commercially available DRAM chip was the 1970 presented by Intel type 1103. It contained 1024 memory cells (1 Kibit ). The principle of the DRAM memory cell has been developed by Robert H. Dennard Thomas J. Watson Research Center on IBM 1966.

Since then, the capacity of DRAM chips has increased by a factor of 1 million, and reduces the access time to a hundredth. Today ( 2011) DRAM chips have capacities of up to 8 GiByte and access time of 6 ns. The production of DRAM memory chips is one of the best-selling segments of the semiconductor industry. With the products is speculation; there exists a spot market.

Initially DRAM memory from individual memory chips (chips) were built in PLCC packages. For 16 KiB of memory ( for example, the Atari 600XL or CBM 8032 ) were 8 memory blocks of the type 4116 (16384 cells to 1 bit) needed. For 64 KiB 8 blocks of type 4164 (C64 -I) or 2 blocks of the type 41464 were (C64 -II) used. IBM PCs were initially sold with 64 KiB than Minimum memory. Here, however, nine blocks were used from the Type 4164; the ninth block saved the parity bits.

Before the SIMMs came on the market, it was, for example 80386 -Mainboards, which could be equipped with 8 MiB RAM, which was constructed from individual chips. This required 72 individual chips of type 411000 (1 Mibit ) are pushed into the socket. This was a tedious and error-prone procedure. If this motherboard be equipped with only 4 MiB of memory, at times significantly cheaper chips (256 KiB) were used instead of type 411000 type 41256, then even had 144 individual chips are plugged into the motherboard: 9 chips found 256 KiB, 16 such groups, each with 9 chips were 4 MiB. Larger chips were therefore soldered into modules that needed considerably less space.

Application

Main memory

Normally, the DRAM is used in the form of memory modules as memory of the processor. DRAMs are often classified according to the type of module interface. In the main uses Double Data Rate Synchronous DRAM (DDR ) have in chronological order, the interface types Fast Page Mode DRAM ( FPM), Extended Data Output RAM ( EDO ) Synchronous DRAM (SDR ) developed. The properties of these types of DRAMs have been standardized by the JEDEC consortium. In addition, existing parallel to SDR / DDR Rambus DRAM interface, which is primarily used in memory for servers.

Special Applications

Special RAM is used as the image and texture memory for graphics cards, for example GDDR3 ( Graphics Double Data Rate SDRAM).

The restriction to a specialty the refresh of the memory cells can be optimized, so you can put this for example in an image memory in the time of retrace. Also, it may be tolerable if a single pixel time, the wrong color displays, one is not so reliant on to take on the worst memory cell of the chip consideration. Therefore, can be - despite the same manufacturing technologies - much faster DRAMs finished.

For special applications, other types have been developed: the Graphics DRAM ( also Synchronous Graphics RAM SGRAM ) is optimized, for example by higher data widths for use on graphics cards, but with recourse to the basic mode of operation, for example, a DDR DRAMs. The precursor of the Graphics RAM were the video RAM ( VRAM) - had to have and then the Window RAM ( WRAM ), the EDO features and a dedicated display port - one optimized for graphics applications Fast Page Mode RAM with two ports instead of one.

For use in network components optimized DRAM types from different manufacturers have the names of Network RAM, Fast Cycle RAM and Reduced Latency RAM receive. In mobile applications such as mobile phones or PDAs, low power consumption is important - this mobile DRAMs to be developed in which, by special circuitry and production technology, the current consumption is lowered. A hybrid role takes the pseudo - SRAM ( other manufacturers also cellular RAM or 1T- SRAM = 1- transistor SRAM ) a: the memory itself is a DRAM that behaves externally as an SRAM. This is achieved by a logic circuit implementing the access mechanism typical SRAM to the DRAM control and in principle necessary for regular refreshing of the dynamic memories is performed by the memory contents contained in the module circuits.

In the early days of the DRAMs, as these were often incorporated into a ceramic DIL package, there were craft solutions, to use them as image sensors for DIY cameras. For this, the metal lid was carefully removed on the ceramic package, including then lay directly - without any sealing compound - of the. Previously, a lens was placed, which abbildete the image precisely on the die surface. If the chip was completely filled at the beginning of exposure to 1, ie all memory capacitors were charged, the charges were discharged at different rates depending on the intensity of incident light. After a certain (exposure ) time, the cells were read and interpreted in 1- bit resolution the image. For grayscale you had to take the same image multiple times with different exposure times. An additional complication came from the fact that the storage cells are arranged for reasons of crosstalk avoidance not just according to their binary addresses, but these address bits are specifically " scrambled ". Therefore, the image data needed for the read-out first with the inverse pattern are brought into the correct alignment. With today's chips is hardly possible, since they are normally embedded in plastic sealing compound; also digital cameras are now widely available and affordable.

Types

There are a variety of DRAM types that have developed historically:

• FPM RAM
• EDO RAM
• SDRAM
• DDR SDRAM
• RDRAM

Are currently a number of non-volatile RAM technologies ( NVRAM) in the development, such as:

• FeRAM
• MRAM
• PCRAM

The storage capacity is measured in bits and bytes.

RAM used as a work memory is often used in the form of memory modules:

• SIMM/PS/2-SIMM
• DIMM / SO -DIMM
• MicroDIMM

When RAM used has virtually always a binary total size.