OpenRISC

OpenRISC is a project of OpenCores developer community. The goal of the project is the development of a highly configurable RISC CPU as open hardware. The so far only completed architecture is the OpenRISC 1000 family (short OR1k ), as 32 ​​- is available and 64- bit version. The design of the OpenRISC 1200 ( OR1200 short ) was the first to be published in the hardware description language Verilog under the GNU Lesser General Public License (GNU LGPL). The firmware and microcode for the processor were provided under the GNU General Public License (GNU GPL). Based on the OpenRISC 1200 a system-on- a-chip variant called ORPSoC ( = OpenRISC Reference Platform System-on- Chip) has been developed. The operation of a Linux system has been successfully tested on both variants. These processors are implemented in an FPGA.

Construction

The design of the OpenRISC 1000 corresponds to a lean implementation of modern RISC architectures with 16 or 32 registers and a fixed instruction length of 32 bits. The 32 - and 64- bit version uses the same instruction set. The design includes all the features that are expected of today's desktop or server processors. These include: virtual memory management, a Secure Virtual Machine, MAC, a SIMD implementation or multiprocessor system operation. The cache size is scalable from 1 to 64 KiB.

Applications

Most applications have been implemented in an FPGA. Initially adopted in 2011 OpenCores an appeal to the first time to produce a OpenRISC 1200 in ASIC technology. Although the OpenRISC -1000 design is considered stable, the performance and the energy consumption is currently not optimized, which is why to this day ( September 2012 ) no ASIC chip was produced.

In addition to the efforts of OpenCores to make a completely free chip, there are commercial implementations. Some companies used the OpenRISC -1200 or ORPSoC design as the basis for their own developments. The following processors are designed on the basis of OpenRISC 1000:

  • BA12, BA14, BA22 from Beyond Semiconductor based directly on the OpenRISC 1200.
  • The OpenRISC 1200 is a functional unit on complex ASIC of Flextronics International and Jennic Limited.
  • Samsung ORPSoC used in the chip - Series B SDP83, SDP92 C, SDP1001/SDP1002 D, and E. This SDP1103/SDP1106 chips serve as the CPU in DTV devices.
  • Cadence Design Systems OpenRISC used as a reference implementation in their documentation.
  • On July 21, 2012, NASA launched a satellite called TechEdSat with a work based on OpenRISC 1200 onboard computer.

Academic recycling

Since all the details are known at OpenRISC due to the open source approach, the architecture is well suited for education, research and hobby developer. The following non-commercial applications are therefore known:

  • A team at the Institute for Integrated Systems at the Technical University of Munich researched on the basis of the OpenRISC architecture and programming multi -processor systems.
  • The British Open Source Hardware User Group conducts events where the FPGA programming is learned or studied on behalf of OpenRISC.

Operating systems and tool chain

In addition to Linux, RTEMS, FreeRTOS and eCos run on the OpenRISC 1000 architecture. The OR32 above port was included with version 3.1 of the Linux kernel into the main development branch and thus is considered stable. A μClinux port is also available, but is not currently developed. In addition to the GNU toolchain uClibc and Busybox was also newlib ported for OpenRISC 1000. A port of LLVM is in development.

Emulators

The OpenRISC Project gives an instruction set simulator is available, which is based on SystemC and on, in the hardware description language Verilog present directly, processor accesses sources. The following virtual machines can emulate a OpenRISC 1000 System:

X86 virtualization Multiply–accumulate operation
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