Flash memory

Flash memory is a digital storage devices; The exact designation is Flash EEPROM. They provide non-volatile storage with low energy consumption. Flash memory are portable and miniaturized, it can, however, contrary to ordinary EEPROM memory with new flash EEPROM bytes, the smallest addressable storage units, do not delete individually. Flash memory is also slower than ordinary read-only memory (ROM).

• 2.1 Saving and Reading
• 2.2 tunnel effect
• 2.3 Note

• 4.1 NAND Flash
• 4.2 NOR flash
• 4.3 disadvantages of the two architectures

• 7.1 Defect Management in Flash / control logic
• 7.2 Defect Management through Software

History

Name and Name

The term originated in accordance Flash an anecdote from the development laboratory of Toshiba 1984 as Shoji Ariizumi, an employee of the project manager Fujio Masuoka, reminded of taking place in blocks deletion of the memory to a camera flash. He therefore proposed flash before name.

History of development

The history of the flash memory is closely connected with the history of the digital camera. The first Compact Flash device with four megabytes of capacity was introduced in 1994 by SanDisk. In 1998, before the first Sony memory stick, they are now also used in Playstations.

Flash memory are imple where information is persistent ( non-volatile) in the smallest space - must be saved - without permanent supply voltage. This also continues to include memory cards for digital cameras and other mobile devices such as mobile phones, smartphones and handhelds. Other designs or devices in which this storage technique is used are USB sticks and MP3 players as well as the already historic DiskOnChip. The latter were used for example for the permanent storage of the firmware in many devices with microcontrollers ( embedded systems, BIOS); increasingly integrated for the same purpose on the microcontroller itself: embedded flash.

Increasingly, in the interest of the use as the main mass storage device in computer systems. Here flash memory can be in the form of Solid State Drives (Eng. solid state drive), the traditional hard disk drives (English hard disk drive ) to replace or supplement (see hybrid hard disks).

Principle of operation

In a flash EEPROM memory information (bits ) in a memory unit ( memory cell) in the form of electric charges on a floating gate or a charge trapping memory element of a metal-insulator- semiconductor field effect transistor ( MISFET ) is stored. In both cases, the charges influence on the gate ( stationary space charges ), as in normal MISFET, the carriers in the underlying area between the source and drain contact ( the so-called channel ), whereby the electrical conductivity of the field effect transistor is influenced thereby and a permanent information storage is possible.

Other than the normal gate MISFETs the floating gate of all the other parts ( the channel region and control gate ) by a dielectric ( usually silicon at present ) is electrically isolated; the potential on the floating gate is therefore basically undefined ( this is also called floating, floating english called ). During a charge-trapping memory which takes an electrically non-conductive layer of silicon nitride, the electrons and holes to be traps (English trapping center) is held stationary. Although the structure established, both variants show significant differences, is the principle of operation of which is held stationary electric charges, which affect a MISFET in its properties, ident in both cases

This information can be stored specifically, but charges must be brought onto the floating gate and the charge trapping structure and can be removed again. This change in the charge state is only possible through quantum physics tunnel effect, which allows electrons to pass through the actual dielectric. As this is only due to large differences in electrical potential across the insulator ( which represents a potential barrier for the charge carriers ) can be effected, the electrical insulation of the floating gate that is introduced charges from the floating gate can not flow and the memory transistor its information long time reserves. In the charge trapping structure is composed of electrically non-conductive insulator is silicon nitride, which is introduced as in the floating gate charges can not easily drain.

In the initial phase of this technique, only two charge states were distinguished, so only one bit per cell might be stored. Meanwhile, the flash EEPROM memory cell, however, multi-level memory cells, in which multiple bits are stored per memory transistor; For this purpose, one uses in the floating gates of different electrical conductivity at different charge states of the transistor and to the charge trapping ability per one bit of information in the drain and the source region stored separately. The reading of two bits per MISFET is done by changing the direction of the readout current in the channel.

Storing and reading

Storage of a bit, in the following is shown only the save process in a floating gate via the floating gate, the actual storage element of the flash field effect transistor. It is situated between the control gate and the source -drain path and is isolated from this as well as from the control gate by an oxide layer, respectively. In the unloaded state of the floating gate a current can flow in the set controlled by the control gate transistor in the source-drain path ( channel). Are placed on the floating gate via the control gate by applying a high positive voltage ( 10-18 V) is electron, then the source -drain path of flow no current also At open transistor, since the negative potential of the electron counteracts on the floating gate of the voltage at the control gate, and thus keeps the flash transistor closed.

The uncharged state is again achieved by the electrons are driven by applying a high negative voltage on the control gate channel path out of the floating gate. It is even possible that the flash transistor falls into the self-conducting state, that is, it even draws power when the control gate voltage is not applied ( over erase ): instead of electrons, the floating gate is now quasi- positive charge carriers ( electron holes, " holes" ) occupied. This is particularly problematic in NOR architectures (see below).

Tunnel effect

The mechanism that lets the electrons through the insulating oxide layer is called Fowler -Nordheim tunneling effect (after its first explorers ), i.e., a flash memory, is to ensure that an interpretable only quantum mechanical effect. In order to increase the probability that electrons tunnel to the floating gate, the method CHE ( channel hot electron Sheet ) is often used: the electrons are accelerated by applying a voltage across the channel, ie between the drain and source, is accelerated and thereby to a higher energy level (hence engl. hot) boosted, so that they (typically 10 V) tunnel even at low voltages between the gate and channel to the floating gate. ( In the image above to program this method - but for an older technology - indicated. )

Note

Whether charged or uncharged floating gate state and each is 0 - or 1- state is considered of the memory cell, is implementation-dependent. But is, by convention, usually one of the floating gate condition, which is produced by blockwise erase, as 0 ( "deleted" ) referred. Accordingly, we referred to the bitwise adjustable condition as 1 (" programmed ").

Control

A flash memory consists of a specific, dependent on the storage size number of individual storage elements. The bytes or words (typically quite up to 64 bits ) can be addressed individually. They can also be written individually in some architectures, whereas in others only larger amounts of data can be programmed at a time. In general, the opposite operation, deleting, but only in larger units called sectors (usually a quarter, eighth, sixteenth, etc., the total storage capacity ) is possible. The logical polarity is not always the same for both implementations exist that implement the programming logic as a logical 0 to 1 transition, and vice versa.

However, a common feature is always that the two operations

• Each represents only the transition in one direction ( 0 to 1 or 1 to 0) and
• (often) only one can work from both bit - selective: the programming.

This means that always only for rewriting an erase operation ( on a byte EEPROM in some architectures, in a sector in flash ) is necessary, and then the desired bit pattern, that is, the desired memory capacity is obtained by programming operations.

Often need to be given (in the form of a sequence of precisely specified to be applied Daten-/Adresspaaren ) to the flash memory for writing to the flash memory special commands. This is a security measure against writing or accidental erasure of memory.

All these detail operations usually happen transparent to the user and the respective application program. There are usually flash memory optimized file systems that implement these procedures. Some flash memory such as USB flash drives also contribute to the operation of the interface to the computer its own microcontroller, on which are wear-leveling algorithms implemented that ensure that even without such an optimized file system and the disk worn out as evenly as possible.

Architectures

On the market are presently two common flash architectures that differ in the nature of the internal connection of the memory cell and hence in the storage density and access speed. Basically, the memory cells are arranged as a matrix, in which are used by a coordinate, the address lines for selecting a row or column of memory cells and the other coordinate data lines leading to the memory cell. The implementation of the data lines represents the main difference between the architecture NAND flash and NOR flash

NAND flash

The memory cells are connected in series in larger groups (for example 1024) (series connection). Which corresponds to the n-channel branch of a NAND gate in the CMOS technology. A group shares one data line. Reading and writing is thus not possible optional, but must always be carried out sequentially in all groups. Due to the lower number of data lines needed NAND Flash less space. As data is read in blocks on disks, NAND flash is suitable in spite of this limitation, as a replacement for disk storage.

The NAND architecture focuses on markets in which it depends on a lot of storage in a small space, less so in low access time.

NOR flash

The memory cells are connected in parallel via data lines - this depending on the precise architecture can be on the source or the drain side. This corresponds to an interconnection, as in the n-channel branch of a NOR gate in CMOS. Access can be optional, and right here. Therefore, the program memory of microcontrollers from NOR flash is set up.

The NOR architecture is based on the replacement of UV - erasable EPROM (which have since replaced by Flash devices and almost hardly be further developed ). In addition, it is here that realize significantly shorter access times: The parallel circuit has the lower resistance between the power source and evaluation.

Disadvantages of the two architectures

Have flash memory a limited lifetime that is specified in a maximum number of erase cycles ( 10,000 to 100,000 cycles for NOR flash and up to two million for NAND Flash). This also corresponds to the maximum number of write cycles, since the memory must be cleared each block by block, before it can be rewritten. This number of cycles is called Endurance ( resistance). Responsible for this limited lifetime, the occurrence of damage in the oxide layer in the area of the floating gate, which causes the flow of the charge.

Another important parameter is the time of error-free data storage, retention.

A further disadvantage is that the write access for the flash memory significantly slower than the read access. Additional delays may arise from the fact that only whole blocks can be deleted.

Techniques

The most important criterion to distinguish between flash techniques, the geometry of the memory cell transistor of the flash, including the following types of cells can be distinguished (this can also apply more of the following characteristics ):

• The split-gate cell
• The ETOX cell, a simplified structure in which the downwardly bent away portion of the control gates of said split gate cell is omitted, the floating gate is charged usually with CHE
• (Uniform Channel Program) UCP- cell, which is usually described in both directions with Fowler -Nordheim tunneling
• NROM cell with charge trapping Save: here is the charge "shot" directly into a zone of the insulator of silicon nitride between the channel and the control gate, in embodiments in which two charge regions (one in source, the other in drain nearby) will be pronounced, so that cell can store two bits at a time. Common in larger NAND memories in the form of vertical NAND structures (V- NAND), which are available since 2002.
• The two-transistor cell: a normal n- channel transistor and a flash transistor in a row. This cell has the disadvantage that it is larger, but is easier to be controlled under certain circumstances for programming and erasing, which may bring with smaller memory sizes in other circuitry area savings.
• Multi-level cell: Here, the flash cell stores not only a bit, but (usually) two, now also four independent bit states. These are coded in conductivity values ​​that are distributed back to the two bits in the readout electronics. The actual doubling the storage capacity is but the significantly longer access time (it has an analog voltage on four levels, compared with two in the binary flash cells are checked ) and a greater error probability ( a change in conductivity by one sixteenth of the maximum difference in conductivity can already the value of the change in the cell stored levels ) counter.

Memory sizes

In early 2009 provide several manufacturers ( Samsung, Toshiba and others) NAND flash memory with 16 gigabytes in SLC technology ( Single Level Cell ) and 32 gigabytes in MLC (Multi Level Cell), NOR flash memory achieves the same time 1 gigabyte storage capacity.

The difference in storage capacity is primarily due, that are executed in NAND flash memory, the data and address lines to the same terminals (pins), i.e., the same connection alternately for data and address transmission used ( "Multiplex " ), while the NOR flash memory devices, they are separated. Thus, the NOR - types can be much faster the data access efficiency, but have significantly more pins and need so that in principle larger housing. In fact, however, at higher capacity, the housing of the NAND type is nearly as large as that of the NOR type, but which is located on the very large memory chip in the interior, not the space required for the connections. However, the package pin at least NAND types are actually connected, the advantage of simpler " wiring " of the block in the device is therefore obtained.

Number of erase cycles

The maximum number of erase cycles of Flash memory varies depending on the manufacturer, technology ( MLC or SLC NAND, NOR) and structural size (50 nm, 34 nm, 25 nm). The manufacturer's instructions are in the range of 3,000 to several 100,000.

The flash memory stores its information on the floating gate. In an erase cycle, the electrons tunnel through the oxide layer. For high voltages are required. This oxide layer surrounding the floating gate, a little damage ( degeneration) in each deletion. Eventually, the insulation is no longer given by the oxide layer, the electrons no longer remain on the floating gate captured, and stored on the memory cell information is lost. However, the failure of a single cell makes a flash memory not long unusable.

Defect management in Flash / control logic

Failures of individual cells are detected by error detection and logging in a protected area. For error detection and correction ( 512 bytes ) are stored additional bits to each block. With this single faulty guard bits are correctable errors over several bits are not reliably detected. The control logic indicates errors that block the driver software can then mark this block as defective. This defect table is located in the so-called spare (reserve ) area of ​​the flash, which is not described in normal operation. The calculation and control of the guard is implemented in the control logic, not in the flash itself. In addition to simple Hamming codes especially BCH codes and Reed -Solomon codes are used.

Defect management by software

To avoid such defects, the driver software ( a special file system ) designed so that they distributed the write and erase operations evenly as possible over the entire memory area of a block and for example not always easy at address 0 begins to write. This is known as wear-leveling algorithms ( German: algorithms for uniform wear ).

Pros and Cons

As a non- volatile storage medium, the flash memory is in competition especially for hard drives and optical media such as DVDs and Blu- ray discs.

The main advantage lies in the improved robustness of the mechanism. Flash memory can be made considerably more robust to hard drives. However, often the life of the plug contacts (USB connector ), the limiting factor.

A further advantage is the permitted higher ambient temperature, the operating temperature of the memory element ( less than 100 ° C ) is not higher than that of modern magnetic layers of the hard disk ( more than 100 ° C).

Benefits: As a flash memory requires no mechanical moving parts, it offers the same a number of advantages over other ROMs: Both the energy consumption and heat generation are lower. Moreover, the memory operates silently and is largely resistant to shocks. By implementing a semiconductor memory results in a light weight and a small size. To achieve a 16 GB microSD card included plastic case and controller data density of 139 GB / cc. The access times are very short compared to other ROMs. This not only improves the performance, it also opens up new fields of application. As a flash memory is used, for example, as a fast buffer memory, for example as ready boost cache. The minimum cost per storage system may face hard drives be lower, for example at cheap netbooks.

Cons: With a volatile memory such as RAM ( Random Access Memory ), the Flash technology despite a lower price per gigabyte not compete because the achievable data rates are significantly lower in Flash. In addition, the access time in the NAND Flash for read and write accesses is significantly greater. In NOR flash, this only applies to the write accesses. The cost per gigabyte of flash memory significantly larger than for hard disks and optical discs. A major problem with the flash memory, the error rate. Sectors are damaged mainly by deletion requests and indescribable with time and are thus defective ( see number of erase cycles ). Regardless permanent bit errors may occur. All of these errors can be concealed by appropriate fault corrective action, but this is expensive and increases the complexity of the flash controller. Nevertheless, it can not prevent a flash memory with time becomes smaller, since the number of usable sectors decreases to. Compared with the life of a hard drive, this effect seems negligible according to recent studies.