Intel iAPX 432

The Intel iAPX 432 was the first 32-bit Intel microprocessor. It was introduced in 1981 as a set of three integrated circuits and was planned as the basic Intel design for the 1980s. Advanced features such as Preemptive multitasking and memory management were implemented in hardware, so the design also called the " Micro Mainframe ".

The data structure supporting the processor is allowed to implement modern operating systems with much less code than ordinary CPUs - 432 instead of the completed a majority of the work in the internal hardware. Compared to other processors, the chip structure has been extremely complex. Intel's engineers succeeded with the former semiconductor technology not to implement the concept in an efficient implementation. The CPU was very slow and expensive, and Intel's plans to replace the x86 architecture by the iAPX 432, ended in economic disaster.

The acronym stood for intel iAPX Advanced Processor architecture, the X came from the Greek letter Chi; but if you APX also indicated Greek, it means architecture.



The 432er project began in 1975 as the i8800 and should be classified in the existing product lines 8008 and 8080. The design was planned from the beginning as a pure 32 -bit design. It should be much more powerful and more complex than the previous Intel processors and still lay far beyond the capabilities of that process technology. The CPU must therefore be split into multiple chips.

The main processor (General Data Processor GDP) consisted of two chips. A chip ( the 43201 ) fetched and decoded the commands, the second ( 43202 ) carried them out. Optional stand with the 43203 Interface Processor (IP) and an I / O controller. Overall, the three-chip team consisted of 250,000 transistors and was therefore one of the most extensive designs of its time. There was thus, for example, the Motorola 68000 of about 68,000 transistors, a third of the microcode.

In 1983, two additional Intel chips for the iAPX 432 Interconnect Architecture, which 43204 Bus Interface Unit ( BIU ) and the 43205 Memory Control Unit ( MCU). With them, multiprocessor systems have been possible with up to 63 nodes.

The failure of the project

Several design features ensured that the iAPX 432 was much slower than it could have been. The two-chip implementation of the GDP this limited to the speed of the wiring on the motherboard. However, this was less of an issue. Far more serious was the lack of caches and registers. Also, the instruction set slowed down the performance because instead of the usual lying on word boundaries (word -aligned ) instructions fixed length, lying on bit boundaries (bit- aligned) instructions of variable length were used. The decoding of the instructions was thus complex and slow. The BIU should support fault-tolerant systems, which brought a significant overhead on the bus with him. 40 percent of the time spent with the bus wait cycles.

Investigations after the project showed that the biggest problem was probably in the compiler, which is used in all cases, the general and slow commands, instead of quick and easy instructions to use at least where it would have been useful. The iAPX 432 knew, for example, a very expensive inter-module procedure call command that the compiler used for all calls. The much faster jump instructions he ignored. Another call was very slow enter_environment with which the memory protection has been established. The compiler called him on for each variable in the system, although the vast majority were running in an existing environment and did not have to be checked. To make the situation worse, call- by-value and not call -by-reference has been used basically what huge memory copies made ​​necessary in many cases.


The teaching was drawn from the failure iAPX 432, that the support of objects at the CPU level leads to a complex design that runs inevitably slow. Since the publication of the iAPX 432 no one has put on the legs a similar design. Indeed, but it looks as if the support of object-orientation was not the problem. The iAPX 432 suffered from problems that would have made slow each chip design.

Intel had large amounts of time and money in the development and marketing of the 432 had invested, set a capable team and it was reluctant to just give up the team after this failure. Under the leadership of new chief designer Glenford Myers, the main processor should be re- designed and then built under a joint venture with Siemens. For this project later was the CPU serial i960, the long period of great popularity in the embedded market enjoyed. In 1990, the responsible team from the i960 and began the development of up to the present day successful P6 core, which debuted in 1995 in the Pentium Pro and later - was sold as Pentium M - in a developed form. Also the Core 2 microarchitecture returned to the Intel after problems with the NetBurst architecture, based on the P6 core.

Non -x86 processors: 4004 | 4040 | 8008 | 8080 | 8085 | iAPX 432 | i860 | i960 | Itanium | Itanium 2

Until 4th Generation: 8086 | 8088 | 80186 | 80188 | 80286 | i386 | i486DX | i486DX2 | DX4 | i486GX | i486SL/SL-NM | i486SX | i486SX2

Pentium Series: Desktop: Pentium (MMX ) | Pentium II | Pentium III | Pentium 4 | Pentium 4 XE | Pentium D | Pentium XE | Pentium Dual-Core

Mobile: Mobile Pentium 4 | Pentium M | Pentium Dual-Core Server: Pentium Pro

Atom series: Atom

Celeron Series: Desktop: Celeron (P6 ) | Celeron ( NetBurst ) | Celeron D | Celeron (Core ) | Celeron Dual- Core Mobile: Mobile Celeron | Celeron M

Core Series: Core Solo | Core Duo | Core 2 | Intel Core i- series: Core i3, Core i5, Core i7 (list)

Xeon Series: Server: Xeon (P6 ) | Xeon ( NetBurst ) | Xeon (Core ) | Xeon (Nehalem )

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