Intel 8085

The Intel 8085 is a 1976 inserted 8 -bit microprocessor from Intel. As a successor to the Intel 8080 he was at this binary - compatible, but integrated clock generator ( 8224 ) and bus controller ( 8228 ) and had a more powerful interrupt handling. The 5 in the name referred to the fact that the processor required only a 5-volt operating voltage. The 8085 was the CPU for computer systems are not very successful, since he was ousted as its predecessor from 8080 Zilog Z80. For use came the chip in various CP / M computers in the training of electricians and a microcontroller in office typewriters, oscilloscopes in the Rover Mars Pathfinder probe.

  • 3.1 Command structure 3.1.1 instruction cycles, machine cycles clock cycles

Specifications

  • Frequency: 5 MHz ( other versions 2, 3, or 6 MHz)
  • Number of transistors: 6,500 at 3 micron feature size
  • Data bus: 8 bits
  • Address bus: 16 bit
  • In the AH version 20 % less power consumption compared to the normal 8085
  • Direct addressable memory of 64 KiB
  • 1.3 microseconds instruction cycle ( 0.8 microseconds when 8085AH -2 / 0.67 microseconds when 8085AH -1)
  • 4 vectored interrupt inputs ( one of which is not maskable and another is a 8080A -compatible interrupt)
  • Decimal, binary and double- precision arithmetic
  • 40 - pin DIL package

In addition to the original Intel is the processor from other manufacturers, some with improved properties made ​​. The fastest 8085 processor comes with 8 MHz from U.S. companies Tundra Semiconductor (→ English).

Construction

Pin assignment and function

(Symbol ) Pin Input (E), Ed (A) function A8 - A15, AH 21-28 A Address bus high-order 8 bits of the memory address or port AD0 - AD7, AL / D0 - D7 12-19 I / O A multiplexed address and data bus ( time division multiplexer ) 1 clock period of a cycle → low byte of an address Second and third clock period → data bus

Signal 1: AD0 - AD7 detail address, is active in the first clock cycle during the first machine cycle. Thus, the address latch is released.

Defined as together with IO / M the current machine cycle

Distinguishes between memory and port access 0 → 1 → memory access port access

0 → CPU has released the bus and expected data from memory or input port 0 ↑ 1 (rising edge) → CPU takes the data from the data bus

0 → CPU indicates that valid data is on the data bus

1 → memory - port modules are ready for data transfer 0 → CPU waits with write or read cycle

1 → another unit is requesting the bus, the CPU releases the bus as soon as the current bus operation is complete.

HLDA ← 0 if HOLD prompt == 0, the CPU A half clock period later takes over the bus again.

General interrupt input for triggering of program interruptions from external signals is enabled or disabled by software

After accepting an INTR used instead of RD → activation of a Interruptbausteines

Which are masked by the commands SIM and DI. Alarm notification for 0-1 transition. Here branches to 3Ch. RST7.5 highest priority of the RSTs, RST5.5 the lowest.

By a reset, the program counter is set to zero. In addition, the HLDA HOLD and flip-flops are reset. During the reset data, address and signal lines are switched to high impedance. Since this is an asynchronous line, the internal registers may enter an undefined state.

Can be used as a system reset. This signal is synchronized with the processor clock.

By running the RIM instruction, the value is stored in the accumulator.

Serial data output is set or reset by a SIM command.

Register

The 8 -bit register may be taken together for 16 -bit instructions to register pairs, these are A / FLAG, B / C, D / E and H / L. The formation of the register pairs is significant at the stack PUSH and POP instructions and addressing and address calculation instructions.

The general purpose register B, C, D and E are essentially logical and arithmetic 8 -bit operations, which are possible with the registers H and L, but should be avoided. The latter registers play in the 16 -bit operations a special role. The results of most operations are available in the accumulator A.

Register pairs

The register pairs are doing special tasks, depending on the type of addressing. Thus, the register pairs B / C and D / E can be used to read in indexed addressing data from the memory or to write there. The pair H / L does not allow this, but it can even be addressed directly written into memory or read from there. Another command allows the direct exchange of the contents of register pairs D / E and H / L, as well as the exchange of the contents of the current stack top ( stack pointer position) with H / L, the content of H / L in the stack pointer and the contents copy of H / L in the program counter. The register pairs can be incremented, decremented, and added to the register pair H / L.

The technique with the register pairs was significantly expanded in the follow-up model 8086.

Status register

In five of the eight state register bits are assigned. These have a conditional jumps and calls, the task of deciding whether a jump or call condition is met. These are the following N (negative ) and S (sign), Z (zero - zero ), H (half carry - half carry) or AC (Auxiliary Carry - auxiliary carry), P ( parity - parity ) and C ( Carry - carry).

Are set, the bits in all the logic and arithmetic 8 -bit operations, but not for copy and exchange commands. Of the 16- bit instructions is only the addition of a register pair to pair H / L is the carry bit. Important for Increment and Decrement commands the absence of the C- bits ( carry), 8- bit operations can overflow are checked only with the Z bit ( Zero ) for 16- bit operations only by downstream OR commands.

Interrupt

The assignment of the interrupt is different depending on read or write access and operation. The register is essentially used to query and review of Interruptzuständen and masking ( blocking ) of individual interrupts. When writing (SIM command) into the bit 6 must register always be 0 in order to change the register, in addition must be set bit 3 (MSE ) to 1 in order to take over, interrupts in bits 0-2.

Interrupts and Reset

Compared to its predecessor, the 8080 interrupt controller has been significantly expanded. In addition to the original interrupt ( by interrupt controller controller ) has the 8085 four additional interrupt inputs. The vectored interrupts and reset control in 8085 at fixed addresses, a concept that was abandoned in the successor types. As of 8086 the Interruptadressen be stored in a table in the first 1024 bytes.

Addressing

The 8085 has an address space of 64 kbytes of memory accesses and 256 addresses for port accesses. The distinction between memory and port access is controlled by an output IO / M, at Port access here is an H at a L. applies to memory accesses As a special feature that lie at port accesses the port address to both AD0 to AD7 as well as to A8 to A15. The lower 8 bits of the address are multiplexed together with the data bus, which means they share the same connections AD0 to AD7. The high-order 8 bits have their own terminals A8 to A15. To indicate that a valid address is present on the bus, the processor outputs at the output ALE ( Address Latch Enable ) from a H. The address can then be stored temporarily in an external memory, this is performed by a negative edge triggered or positive pulsgetriggerter external memory device (usually, a D flip-flop ) the content of the AD0- AD7 and outputs it to the low order eight bits of the pure address bus. In some circuits, the high-order address byte and A8 to A15 is also cached to improve the time response, even if it actually is not mandatory for the 8085.

The outputs S0 and S1 of the status of the current machine cycle is beyond output (see table above). Due to external modules can hereby be established an address extension, but does not reach the segment control the successor models.

Machine instructions

Command structure

An assembly language program consists of a sequence of 8 - bit instructions, in exceptional cases, commands that consist of two consecutive bytes. The execution is always sequentiell.Bei a word length of 8 bit 256 different commands are possible, of which only 246 are implemented during 8085. For each instruction, the first byte contains the operation code ( op code ), so it is the operator. Often the operand, eg, the accumulator, already implicitly included, then the whole command is only one byte long. The total command can also be 2 or 3 bytes long:

The command sequence in the microprocessor corresponding to the von Neumann scheme. First, the instruction to which the contents of the Befehlszählregisters ( program counter, PC, IC ) indicates is fetched and stored in the instruction decoder. There it is then decoded.

A command requires 1 to 5 machine cycles ( machine cycle, cycles of operation ) M1 - M5 A machine cycle consists of 3 to 6 clock cycles ( States, operation steps ) T1 - T6

Depending on the command, a different number of machine cycles is executed. This is recognized in the first machine cycle ( instruction fetch, FETCH cycle).

Instruction cycles, machine cycles clock cycles

The time period for one machine cycle is about 3-6 bars on "old" microprocessors. Typical machine cycles that can occur within one instruction cycle are:

Instruction set

Transfer commands Register after register

Memory, peripheral registers by

Constant by register pair

Register for memory, peripherals

Constant according to registers, memory

Arithmetic instructions

Logical operations

Register instructions rotate accumulator

Carry bit instructions

Jump instructions

Unconditional jumps

Conditional jumps

Subroutine treatment Subroutine calls

Return instructions

Program interruption

Mask commands

Other command

Example Program

Simple program with input and output

; A comment begins with a semicolon or a semicolon, the text behind it is ignored by the assembler   mark:; a brand is marked with a colon     star: IN 01; reading the ports 01         OUT 02; Output on Port 02         JMP star; Jump back to beginning of program complex program

This program provides a small running light dar. It can be combined with bit D7 of the input module ON and OFF switch. Bit D6, the rotation direction is determined (right or left) and bit D0, one can choose between two speeds. Pause should be set to 0 and bit D7 to 1.

, The main program         MVI B, 01; initial value for rotation   mei: IN 01, A? (Bit D7 = 1?)         ANI 80; bitmask for D7         JZ mei; -> MEI, if not "ON"         Drive running light; MOV A, B         OUT 02         IN 01, left rotation? (Bit D6 = 1?)         ANI 40; bitmask for D6         JZ rr, - > RR, if not left rotation         MOV A, B         RLC, next left rotation         MOV B, A   mv: IN 01; rapid rotation? (Bit D0 = 1?)         ANI 01; bitmask for bits D0         JZ ze2; -> ZE2 slowly when         Otherwise call subroutine ZE1; CALL ze1         JMP mei    , Right rotation   rr: MOV A, B         RRC, next right rotation         MOV B, A         JMP mv    ; Time loop 1   ze1: LXI D, 0001; invite Z   MZ1: DCX D, Z: = Z-1         MOV A, D, Z = 0?         ORA e         JNZ MZ1; -> MZ1, 0 otherwise         RET; jump back ...    ; Time loop 2   ze2: LXI D, 0006; invite Z   MZ2: DCR D, Z: = Z-1         MOV A, D, Z = 0?         ORA e         JNZ MZ2; -> MZ2, 0 otherwise         JMP mei Outputting to the store

; Tables:        , tab1         ORA 0e100; Table Address         DB 01,02,04,08,10,20,40,80,00        , tab2:         ORG 0e200; Table Address         DB 01,03,07,0 F, 1F, 3F, 7F, 0FF, 00    , The main program         ORA 0e000; starting address         LXI SP, 0fc32; Load stack pointer with the address FC32                    , a zero must be preceded by at Hex -letter         LC; delete label table    , Program function:                    , Marks or labels are initialized with a colon   star: IN 01, the hex value from the input port to the                    , Address 01 is loaded into the accumulator         ANI 01; AND of the hex value 01 with the battery         JZ sch1; If the zero flag is set, jump to the label " sch1 "         JNZ SCH 2; If the zero flag is not set, jump to the label " SCH 2 "    ; First subroutine   sch1: LXI H, 0e100; Loads the register pair HL with the address e100   loo1: MOV A, M, and the value which is in the memory cell by the register pair                    , HL is addressed in the battery         ORA A; ORing the batteries with itself         JZ star; If the zero flag is set, jump to the label " star"         OUT 02, The contents of the accumulator is passed to the output port         INX H; Table address in HL is increased by 1         CALL 0895; UP call                    , UP for a time loop 0.2 seconds         JMP loo1, repeat the program area, jump by " loo1 "    , 2 subroutine   SCH 2: LXI H, 0e200; Loads the register pair HL with the address E200   loo2: MOV A, M, and the value which is in the memory cell by the register pair                    , HL is addressed in the battery         ORA A; ORing the batteries with itself         JZ star; If the zero flag is set, jump to the label " star"         OUT 02, The contents of the accumulator is passed to the output port         INX H; Table address in HL is increased by 1         CALL 0895; UP call                    , UP for a time loop 0.2 seconds         JMP loo2, repeat the program area, jump by " loo2 "     stop: stop JMP; infinite loop to continue the event of an error of                    , To prevent the program. 8085 Software Simulator

For the operating systems Microsoft Windows and Linux, there is, among other things the freely available open source simulator GNUSim8085, which is developed and distributed under the GNU GPL.

Peripheral Devices

8-bit Mask (computing) Intel 8086 Assembly language#Assembler List of Intel microprocessors Intel 4040 Intel iAPX 432 Intel i860 Itanium Pentium 4 Pentium D Pentium D#Smithfield XE Pentium Dual-Core Pentium M Intel Pentium Dual-Core Pentium Pro List of Intel Core i7 microprocessors
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