The term microarchitecture in German about arithmetic unit, called the concrete, internal processor implementation of a CPU with a given instruction set architecture. He explicitly refers not to the production- technical realization of a CPU, but on the internal processes in the processing of commands on register-transfer level, or at a logical level. For example, superscalar implementation of a CPU is only a kind of realization of their microarchitecture, whereas terms such as VLIW and EPIC designate different paradigms in the design of an instruction set architecture.
The implemented in a processor instruction set architecture allows not forcibly draw conclusions about the microarchitecture used. In practice, micro- architectures are often designed with a view to a given instruction set architecture, such as in order to preserve compatibility with previous models of a CPU. The differences to the micro-architecture of its predecessor, it can sometimes be considerable. As an example, the x86 CPUs Pentium and Pentium Pro are mentioned, their instruction sets - apart from a couple of extensions with the Pentium Pro - hardly differ, but their micro- architectures are fundamentally different.
The design goals of a new or the enhancement of an existing microarchitecture can be numerous. They depend on the later use of the CPU, sometimes from marketing in general. In the foreground is usually the fastest possible execution of a program. However, aspects such as cost-effective production, energy consumption, scalability, extensibility and maintainability can be design goals. This is particularly evident again the example of x86-compatible CPUs: While the market leader Intel and AMD x86 trim their microarchitectures primarily on high execution speeds, try to minimize manufacturers such as Transmeta and VIA in far greater extent, manufacturing cost and power consumption. Thus, the microarchitecture of standing in the tradition of WinChip VIA C3 is kept particularly simple for this purpose, whereas Transmeta a microarchitecture with a kind of highly specialized VLIW CPU used when Crusoe and the Efficeon that performs a so-called code - morphing software, which ultimately responsible for the execution of the actual x86 code draws.
A completely different approach is the instruction set architecture from the outset to design so that design objectives in the implementation of a suitable micro-architecture are particularly easy to implement. Such approaches are of course only when the CPU is possible developments whose instruction set architecture requires no backwards compatibility. Intel has taken this route in the development of Itanium CPU in their design as simple as possible in-order instruction execution stood in the foreground, which can save energy and chip area, and not least also increase the execution speed. The price that the Itanium has to pay for this simplified instruction execution, is the elaborate compiler.
Processor Architectures word width: 1 -bit architecture | bit-slice architecture | 4 -bit architecture | 8- bit architecture, | 16- bit architecture, | 32- bit architecture, | 64 -bit architecture
Processor instruction set architectures based on structure: CISC | EPIC | NISC | RISC | VLIW | microarchitecture
Processor architectures for optimization purposes: (main) processor | GPU | GPGPU | Sound Processor | Math Processor | Network processor | physics accelerator
X86 microarchitectures: 8086 | 80186 | 80286 | 80386 | 80486 | P5 | P6 | NetBurst | Core ( Penryn ) | Nehalem ( Westmere ) | Sandy Bridge ( Ivy Bridge ) | Haswell ( Broadwell ) | Atom
Non -x86 microarchitectures: MCS -48 | MCS -51 | Itanium | Itanium 2
GPU microarchitectures: Larrabee
- Computer Architecture